M12L16161A_05中文资料

Revision History

Revision 0.1 (Oct. 23 1998) -Original

Revision 0.2 (Dec. 4 1998) -Add 200MHZ

Revision 1.0 (Dec. 10 1999) -Delete Preliminary -Rename the filename

Revision 1.1 (Jan. 26 2000) -Add –5.5 Spec.

Revision 1.2 (Apr. 25 2000)

-Correct error typing of C1 dimension

Revision 1.3 (Nov. 27 2000)

-P5 Number of valid output data CAS Latency 3Æ 2ea -P17. P19. P21 Read Command shift right 1CLK -P15. P19. P20 Precharge Command shift left 1CLK

Revision 1.4 (Feb. 22 2001)

-P6 modify tOH –6(2ns) & -7(2ns)

Revision 1.5 (Jun. 4 2001) -P3. P4 modify DC current

Revision 1.6(Sep. 7 2001) -P5 modify AC parameters

Revision 1.7 (Mar. 20 2002)

-P28 C1(Nom)=0.15mmÆ0.127mm -P28 delete symbol=ZD

Revision 1.8 (Dec. 16 2003)

-Modify stand off=0.051~0.203mm

Revision 1.9 (Mar. 05 2004)

-Correct typing error of timing (tRC; tRP;tRCD) -Add tRRD timing chart

Revision 2.0 (May. 10 2005)

Add “Pb-free” to ordering information

Revision 2.1 (Jul. 07 2005)

-Modify ICC1, ICC2N, ICC3N, ICC4, ICC5 spec -Delete –5.5, -6, -8, -10 AC spec

Revision 2.2 (Oct. 06 2005) -Add 60V FBGA

Revision 2.3 (Nov. 15 2005)

-Modify VFBGA 60Ball Total high spec

Revision 2.4 (May. 03 2007)

- Delete BGA ball name of packing dimensions

512K x 16Bit x 2Banks

SDRAM

FEATURES

Synchronous DRAM

z z z z

JEDEC standard 3.3V power supply

LVTTL compatible with multiplexed address Dual banks operation

MRS cycle with address key programs - CAS Latency (2 & 3 )

- Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave)

All inputs are sampled at the positive going edge of the system clock

Burst Read Single-bit Write operation DQM for masking Auto & self refresh

32ms refresh period (2K cycle)

GENERAL DESCRIPTION

The M12L16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

z z z z z

ORDERING INFORMATION

Part NO. M12L16161A-5TG M12L16161A-7TG M12L16161A-7BG

MAX Freq. 200MHz 143MHz 143MHz

PACKAGECOMMENTSPIN CONFIGURATION (TOP VIEW)

VDDDQ0DQ1VSSQDQ2DQ3VDDQDQ4DQ5VSSQDQ6DQ7VDDQLDQM

CASCSBAA10/APA0A1A2A3VDD

VSSDQ15DQ14VSSQDQ13DQ12VDDQDQ11DQ10VSSQDQ9DQ8VDDQN.C/RFUUDQMCLKCKEN.CA9A8A7A6A5A4VSS

50PIN TSOP(II) (400mil x 825mil)(0.8 mm PIN PITCH)

FUNCTIONAL BLOCK DIAGRAM

PIN FUNCTION DESCRIPTION

Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic.

Isolated power supply and ground for the output buffers to provide improved noise immunity.

This pin is recommended to be left No Connection on the device.

DQ0 ~ 15 VDD/VSS VDDQ/VSSQ N.C/RFU

Data Input / Output Power Supply/Ground Data Output Power/Ground No Connection/

Reserved for Future Use

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage temperature Power dissipation Short circuit current

Symbol

Value

Unit V V

VIN,VOUT -1.0 ~ 4.6 VDD,VDDQ -1.0 ~ 4.6 TSTG -55 ~ + 150

PDIOS

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA=0 to 70°C)

Parameter

Supply voltage

Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current

Symbol

Min

Typ

Max

Unit

Note

VDD,VDDQVIHVDDVILVOHIOH =-2mA VOLIOL = 2mA IILIOL

Note : 1.VIH (max) = 4.6V AC for pulse width ≤ 10ns acceptable.

2.VIL (min) = -1.5V AC for pulse width ≤ 10ns acceptable.

3.Any input 0V≤ VIN ≤ VDD+ 0.3V, all other pins are not under test = 0V. 4.Dout is disabled, 0V ≤ VOUT ≤ VDD.

CAPACITANCE (VDD = 3.3V, TA = 25°C, f = 1MHz)

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C VIH(min)/VIL(max)=2.0V/0.8V)

Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min).

2.Refresh period is 32ms. Addresses are changed only one time during tCC(min).

AC OPERATING TEST CONDITIONS (VDD=3.3V±0.3V,TA= 0 to 70°C)

Parameter

Input levels (Vih/Vil)

Input timing measurement reference level Input rise and fall time

Output timing measurement reference level Output load condition

Value 2.4 / 0.4 1.4 tr / tf = 1 / 1

1.4 See Fig.2

Unit V V ns V

1.4V

Ω

(Fig.1) DC Output Load circuit

(Fig.2) AC Output Load Circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.

-5 Min Max5 7

1000

-7 Min 7 8.6

Max 1000

Unit

Note

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Parameter

CLK cycle time CLK to valid

output delay

CAS Latency =3 CAS Latency =2 CAS Latency =3 CAS Latency =2

Symbol tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ

Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z

CAS Latency =3 CAS latency =2

ns

*All AC parameters are measured from half to half.

Note: 1.Parameters depend on programmed CAS latency.

2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.

3.Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the parameter.

FREQUENCY vs. AC PARAMENTER RELATIONSHIP TABLE

M12L16161A-5T(G)

Frequency

(Unit: number of clock)

tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL CAS

Latency 55ns 40ns 15ns 10ns 15ns 5ns 5ns 10ns

M12L16161A-7T(G)

Frequency

(Unit: number of clock)

tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL CAS

Latency 63ns 42ns 20ns 14ns 20ns 7ns 7ns 14ns

Note : 1. tRDL≥16.7ns is recommended for M12L16161A.

Mode Register

11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 JEDEC Standard Test Set (refresh counter test) 11 10 9 8 7 6 5 4 3 2 1 0 x x 1 0 0 LTMODE WT BL Burst Read and Single Write (for Write Through Cache) 11 10 9 8 7 6 5 4 3 2 1 0 1 0 Use in future 11 10 9 8 7 6 5 4 3 2 1 0

x x x 1 1 v v v v v v v Vender Specific

Mode Register Write

Burst Length and Sequence

(Burst of Two)

Starting Address Sequential Addressing Interleave Addressing (column address A0 binary) Sequence (decimal) Sequence (decimal)

(Burst of Four)

Starting Address Sequential Addressing Interleave Addressing

(column address A1-A0, binary) Sequence (decimal) Sequence (decimal)

(Burst of Eight)

Starting Address Sequential Addressing Interleave Addressing

(column address A2-A0, binary) Sequence (decimal) Sequence (decimal)

0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5

4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2

Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 1Mx16 divice.

POWER UP SEQUENCE

1.Apply power and start clock, attempt to maintain CKE= “H”, L(U)DQM = “H” and the other pin are NOP condition at the inputs. 2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3.Issue precharge commands for all banks of the devices. 4.Issue 2 or more auto-refresh commands.

5.Issue mode register set command to initialize the mode register. Cf.)Sequence of 4 & 5 is regardless of the order.

SIMPLIFIED TRUTH TABLE

(V= Valid, X= Don’t Care, H= Logic High , L = Logic Low)

Note:

1. OP Code: Operation Code

A0~ A10/AP, BA: Program keys.(@MRS)

2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by “Auto”. Auto / self refresh can be issued only at both banks idle state. 4. BA: Bank select address.

If “Low”: at read, write, row active and precharge, bank A is selected. If “High”: at read, write, row active and precharge, bank B is selected.

If A10/AP is “High” at row precharge, BA ignored and both banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read /write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes

Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3, Burst Length=1

CLOCK

CKE

RAS

ADDR

BAA10/APDQ

DQM

2. Bank active & read/write are controlled by BA.

BA

Active & Read/Write

*Note: 1. All inputs expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.

3.Enable and disable auto precharge function are controlled by A10/AP in read/write command.

A10/AP 0

BA 0 1

1

0 1

4.A10/AP and BA control bank precharge when precharge command is asserted.

A10/AP

BA

precharge

Operation

Disable auto precharge, leave bank A active at end of burst. Disable auto precharge, leave bank B active at end of burst. Enable auto precharge, precharge bank A at end of burst. Enable auto precharge, precharge bank B at end of burst.

Bank Bank Both

Power Up Sequence

CLOCK

CKE

ADDR

BA

A10/AP

DQ

WE

DQM

Row Active

: Don't care

Read & Write Cycle at Same Bank @Burst Length = 4

QC

(A-Bank)

Read(A-Bank)

(A-Bank)

(A-Bank)

Write(A-Bank)

(A-Bank)

: Don't care

*Note: 1.Minimum row cycle times is required to complete internal DRAM operation.

2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock.

3.Access time from Row active command. tcc*(tRCD +CAS latency-1)+tSAC 4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst) Burst can’t end in Full Page Mode.

Page Read & Write Cycle at Same Bank @ Burst Length=4

CLOCKCKE

ADDRBA

A10/AP

CL=2DQ

CL=3

DQM

Row Active(A-Bank)

(A-Bank)(A-Bank)(A-Bank)(A-Bank)

(A-Bank)

*Note :1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus

contention.

2.Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.

3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.

Page Read Cycle at Different Bank @ Burst Length=4

CLOCK

CKE

ADDR

BA

A10/APCL=2DQ

CL=3

DQM

(B-Bank)

*Note: 1.CScan be don’t cared when RAS, CAS and WE are high at the clock high going dege.

2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.

Page Write Cycle at Different Bank @Burst Length = 4

CLOCK

CKECS

ADDRBA

A10/APDQ

WE

DQM

(A-Bank)

(B-Bank)

*Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.

2.To interrupt burst write by row precharge, both the write and the precharge banks must be the same.

Read & Write Cycle at Different Bank @ Burst Length = 4

*Note: 1.tCDL should be met to complete write.

Read & Write Cycle with auto Precharge @ Burst Length =4

CLOCK

CKE

CAS

ADDR

BA

A10/APCL=2DQ

CL=3

DQM

( B - Bank )

: D o n ' t C a r e

*Note: 1.tCDL Should be controlled to meet minimum tRAS before internal precharge start

(In the case of Burst Length=1 & 2 and BRSW mode)

Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4

CLOCK

CKE

A

DDRBA

A10/AP

DQWE

DQM

Read DQM

Write

Suspension

:Don't Care

*Note:1.DQM is needed to prevent bus contention.

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