ADUM1230BRWZ中文资料

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Isolated Half-Bridge Driver,

0.1 A Amp Output

ADuM1230

GENERAL DESCRIPTION

The ADuM12301 is an isolated half-bridge gate driver that employs Analog Devices’ iCoupler® technology to provide independent and isolated high-side and low-side outputs. Combining high speed CMOS and monolithic transformer technology, this isolation component provides outstanding performance characteristics superior to optocoupler-based solutions.

By avoiding the use of LEDs and photodiodes, this iCoupler gate drive device is able to provide precision timing characteristics not possible with optocouplers. Furthermore, the reliability and performance stability problems associated with optocoupler LEDs are avoided.

In comparison to gate drivers employing high voltage level translation methodologies, the ADuM1230 offers the benefit of true, galvanic isolation between the input and each output. Each output may be operated up to ±700 VP relative to the input, thereby supporting low-side switching to negative voltages. The differential voltage between the high-side and low-side can be as high as 700 VP.

As a result, the ADuM1230 provides reliable control over the switching characteristics of IGBT/MOSFET configurations over a wide range of positive or negative switching voltages.

1

FEATURES

Isolated high-side and low-side outputs

High-side or low-side relative to input: ±700 VPEAKHigh-side/low-side differential: 700 VPEAK0.1 A peak output current

High frequency operation: 5 MHz max

High common-mode transient immunity: >50 kV/μs High temperature operation: 105°C Wide body, 16-lead SOIC

UL1577 2500 V rms input-to-output withstand voltage

APPLICATIONS

Isolated IGBT/MOSFET gate drives Plasma displays Industrial inverters

Switching power supplies

Protected by U.S. Patents 5,952,849 6,873,065, and other pending patents.

FUNCTIONAL BLOCK DIAGRAM

VIAVIBVDD1GND1DISABLENCNCVDD1DDAOAADDBOBB

05460-001

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

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ADuM1230

Absolute Maximum Ratings............................................................5 ESD Caution...................................................................................5 Pin Configuration and Function Descriptions..............................6 Typical Performance Characteristics..............................................7 Application Notes..............................................................................8 Common-Mode Transient Immunity........................................8 Typical Application Usage............................................................9 Outline Dimensions.......................................................................10 Ordering Guide..........................................................................10

TABLE OF CONTENTS

Features..............................................................................................1 Applications.......................................................................................1 General Description.........................................................................1 Functional Block Diagram..............................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Electrical Characteristics.............................................................3 Package Characteristics...............................................................4 Regulatory Information...............................................................4 Insulation and Safety-Related Specifications............................4 Recommended Operating Conditions......................................4

REVISION HISTORY

12/05—Rev. Sp0 to Rev. A

Changes to Figure 1 and Note 1......................................................1 Added Typical Application Usage Section....................................9 Inserted Figure 14.............................................................................9

5/05—Revision Sp0: Initial Version

Rev. A | Page 2 of 12

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ADuM1230

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 12 V ≤ VDDA ≤ 18 V, 12 V ≤ VDDB ≤ 18 V. All min/max

specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 5 V, VDDA = 15 V, VDDB = 15 V. Table 1.

Parameter

DC SPECIFICATIONS

Input Supply Current, Quiescent

Output Supply Current, A or B, Quiescent Input Supply Current, 10 Mbps

Output Supply Current, A or B, 10 Mbps Input Currents

Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages

Logic Low Output Voltages

Output Short-Circuit Pulsed Current1SWITCHING SPECIFICATIONS Minimum Pulse Width2

Maximum Switching Frequency3Propagation Delay4

Change vs. Temperature

Pulse Width Distortion, |tPLH tPHL| Channel-to-Channel Matching, Rising or Falling Edges5

Channel-to-Channel Matching, Rising vs. Falling Edges6

Part-to-Part Matching, Rising or Falling Edges7Part-to-Part Matching, Rising vs. Falling Edges8Output Rise/Fall Time (10% to 90%)

Short-circuit duration less than 1 second. Average power must conform to the limit shown under the Absolute Maximum Ratings. The minimum pulse width is the shortest pulse width at which the specified timing parameters are guaranteed. 3

The maximum switching frequency is the maximum signal frequency at which the specified timing parameters are guaranteed. 4

tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5

Channel-to-channel matching, rising vs. falling edges is the magnitude of the propagation delay difference between two channels of the same part when the inputs are either both rising edges or falling edges. The supply voltages and the loads on each channel are equal. 6

Channel-to-channel matching, rising or falling edges is the magnitude of the propagation delay difference between two channels of the same part when one input is a rising edge and the other input is a falling edge. The supply voltages and loads on each channel are equal. 7

Part-to-part matching, rising or falling edges is the magnitude of the propagation delay difference between the same channels of two different parts when the inputs are either both rising or falling edges. The supply voltages, temperatures, and loads of each part are equal. 8

Part-to-part matching, rising vs. falling edges is the magnitude of the propagation delay difference between the same channels of two different parts when one input is a rising edge and the other input is a falling edge. The supply voltages, temperatures, and loads of each part are equal.

12

Symbol

IDDI (Q) IDDA (Q), IDDB (Q)IDDI (10) IDDA (10), IDDB (10)

IIA, IIB, IDISABLEVIH VIL

VOAH, VOBH

Min Typ Max Unit Test Conditions 4.0 mA 8.0 mA CL = 200 pF

10 +0.01 +10 μA 0 ≤ VIA, VIB, VDISABLE ≤ VDD12.0 V 0.8 V

IOA, IOB = 1 mA VDDA 0.1, VDDA, VDDB

VDDB 0.1

VOAL, VOBL IOA, IOB = 1 mA IOA (SC), IOB (SC)100 PW 100 ns CL = 200 pF 10 Mbps CL = 200 pF tPHL, tPLH 97 124 160 ns CL = 200 pF 100 ps/°C PWD 8 ns CL = 200 pF CL = 200 pF CL = 200 pF CL = 200 pF CL = 200 pF tR/tF CL = 200 pF

Rev. A | Page 3 of 12

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ADuM1230

PACKAGE CHARACTERISTICS

Table 2.

Parameter

Resistance (Input-to-Output)1Capacitance (Input-to-Output)1Input Capacitance

IC Junction-to-Ambient Thermal Resistance

1

Symbol RI-O CI-O CIθJCaMin Typ Max Unit Test Conditions 1012 2.0 pF f = 1 MHz 4.0 76

The device is considered a 2-terminal device: Pins 1 through 8 are shorted together, and Pins 9 through 16 are shorted together.

REGULATORY INFORMATION

The ADuM1230 is approved, as shown in Table 3. Table 3.

UL1

Recognized under 1577 component recognition program

1

In accordance with UL1577, each ADuM1230 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA).

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 4.

Parameter

Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage)

Minimum Internal Gap (Internal Clearance)

Tracking Resistance (Comparative Tracking Index) Isolation Group

Symbol

L(I01) L(I02) CTI

Value 2500 7.7 min 8.1 min 0.017 min >175 IIIa

Unit V rms mm mm mm V

Conditions

1 minute duration

Measured from input terminals to output terminals, shortest distance through air

Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1

Material Group (DIN VDE 0110, 1/89, Table 1)

RECOMMENDED OPERATING CONDITIONS

Table 5.

Parameter

Operating Temperature Input Supply Voltage1Output Supply Voltages1

Input Signal Rise and Fall Times

Common-Mode Transient Immunity, Input-to-Output2Common-Mode Transient Immunity, Between Outputs2Transient Immunity, Supply Voltages2

12

Symbol Min Max Unit TA 40 +105 °C VDD14.5 5.5 V VDDA, VDDB12 18 V 1 ms kV/μs kV/μs kV/μs

All voltages are relative to their respective ground.

See the Common-Mode Transient Immunity section for transient diagrams and additional information.

Rev. A | Page 4 of 12

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ADuM1230

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter

Storage Temperature Ambient Operating Temperature

Input Supply Voltage1Output Supply Voltage1Input Voltage1Output Voltage1Input-Output VoltageOutput Differential Voltage3

Output DC Current Common-Mode Transients4

All voltages are relative to their respective ground.

Input-to-output voltage is defined as GNDA GND1 or GNDB GND1. 3

Output differential voltage is defined as GNDA GNDB. 4

Refers to common-mode transients across any insulation barrier. Common-mode transients exceeding the Absolute Maximum Ratings can cause latch-up or permanent damage.

12

Symbol TST TA VDD1

VDDA, VDDBVIA, VIBVOA, VOB

Min 55 40 Max +150 +105 Unit °C °C

2

0.5 +7.0 V V 0.5 VDDI + 0.5 V 0.5 VDDA + 0.5,V

VDDB + 0.5

VPEAKVPEAK

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Ambient temperature = 25°C, unless otherwise noted.

IOA, IOBmA kV/μs

Table 7. ADuM1230 Truth Table (Positive Logic)

VIA/VIB Input VDD1 State DISABLE VOA/VOB Output

H Powered L H L Powered L L X Unpowered X L L

Notes

Output returns to input state within 1 μs of VDDI power restoration.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 5 of 12

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ADuM1230

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VIA

VIBVDD1GND1DISABLENCNCVDD1VDDAVOAGNDA

NCNC

VDDBVOB

05460-002

GNDB

NC = NO CONNECT

Figure 2. Pin Configuration

Note that Pin 3 and Pin 8 are internally connected. Connecting both to VDD1 is recommended. Pin 12 and Pin 13 are floating and should be left unconnected.

Table 8. Pin Function Descriptions

Pin No. Mnemonic IAIBDD115 DISABLE 6, 7, 12, 13 NC DD1BOBDDB AOADDA

Function Logic Input A. Logic Input B.

Input Supply Voltage, 4.5 V to 5.5 V. Ground Reference for Input Logic Signals.

Input Disable. Disables the isolator inputs and refresh circuits. Outputs take on default low state. No Connect.

Input Supply Voltage, 4.5 V to 5.5 V. Ground Reference for Output B. Output B.

Output B Supply Voltage, 12 V to 18 V. Ground Reference for Output A. Output A.

Output A Supply Voltage, 12 V to 18 V.

Rev. A | Page 6 of 12

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ADuM1230

6

129

TYPICAL PERFORMANCE CHARACTERISTICS

5

PROPAGATION DELAY (ns)

128

127

4

CURRENT (

mA)

3126

125

2

1124

05460-003

4

DATA RATE (Mbps)

10

15

OUTPUT SUPPLY VOLTAGE (V)

18

05460-00605460-007

123

12

Figure 3. Typical Input Supply Current Variation with Data Rate

1816

128129

Figure 6. Typical Propagation Delay Variation with Output Supply Voltage (Input Supply Voltage = 5.0 V)

1412CURRENT (mA)

108642

05460-004

PROPAGATION DELAY (ns)

127

126

125

1245.0

OUTPUT SUPPLY VOLTAGE (V)

5.5

4

DATA RATE (Mbps)

10

123

4.5

Figure 4. Typical Output Supply Current Variation with Data Rate

135

Figure 7. Typical Propagation Delay Variation with Input Supply Voltage

(Output Supply Voltage = 15.0 V)

PROPAGATION DELAY (n

s)

130

125

120

–200

204060TEMPERATURE (°C)

80100120

05460-005

115–40

Figure 5. Typical Propagation Delay Variation with Temperature

Rev. A | Page 7 of 12

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ADuM1230

The transient magnitude of the sinusoidal component is given by

dVCM/dt = 2πf V0

The ADuM1230’s ability to operate correctly in the presence of sinusoidal transients is characterized by the data in Figure 9 and Figure 10. The data is based on design simulation and is the maximum sinusoidal transient magnitude (2πf V0) that the ADuM1230 can tolerate without an operational error. Values for immunity against sinusoidal transients are not included in Table 5 because measurements to obtain such values have not been possible.

200180160

TRANSIENT IMMUNITY (kV/µs)

140120100

806040200

250

500

75010001250FREQUENCY (MHz)

1500

1750

2000

05460-01205460-013

APPLICATION NOTES

COMMON-MODE TRANSIENT IMMUNITY

In general, common-mode transients consist of linear and sinusoidal components. The linear component of a common-mode transient is given by

VCM, linear = (ΔV/Δt) t

where ΔV/Δt is the slope of the transient shown in Figure 11 and Figure 12.

The transient of the linear component is given by

dVCM/dt = ΔV/Δt

The ADuM1230’s ability to operate correctly in the presence of linear transients is characterized by the data in Figure 8. The data is based on design simulation and is the maximum linear transient magnitude that the ADuM1230 can tolerate without an operational error. This data shows a higher level of robustness than what is shown in Table 5 because the transient immunity values obtained in Table 5 use measured data and apply allowances for measurement error and margin.

300

250TRANSIENT IMMUNITY (kV/µs)

200

150

200

100

TRANSIENT IMMUNITY (kV/µs)

50

180160140

12010080

Figure 9. Transient Immunity (Sinusoidal Transients),

27°C Ambient Temperature

–200

2040

TEMPERATURE (°C)

6080100

05460-011

0–40

Figure 8. Transient Immunity (Linear Transients) vs. Temperature

604020

00

250

500

75010001250FREQUENCY (MHz)

1500

1750

2000

The sinusoidal component (at a given frequency) is given by

VCM, sinusoidal = V0sin(2πft) where:

V0 is the magnitude of the sinusoidal. f is the frequency of the sinusoidal.

Figure 10. Transient Immunity (Sinusoidal Transients),

100°C Ambient Temperature

Rev. A | Page 8 of 12

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ADuM1230

VDDAANDVGNDAAND GNDVGND

05460-008

Figure 11. Common-Mode Transient Immunity Waveforms—Input to Output

VDDA/VGNDA/GNDVDDA/VGNDB/GND

05460-009

Figure 12. Common-Mode Transient Immunity Waveforms—Between Outputs

VDDA/VDDB

VDD t

VDDA/VDDBGNDA/GNDB

GNDA/GNDB

05460-010

Figure 13. Transient Immunity Waveforms—Output Supplies

TYPICAL APPLICATION USAGE

The ADuM1230 is intended for driving low gate capacitance transistors (200 pF typically). Most high voltage applications involve larger transistors than this. To accommodate these situations, users can choose either a gate driver with a stronger output stage or the buffer configuration with the ADuM1230, as shown in Figure 14. In many cases, the buffer configuration is the less expensive of the two options and provides the greatest amount of design flexibility. The precise buffer/high voltage transistor combination can be selected to fit the application’s

needs.

Figure 14.

Rev. A | Page 9 of 12

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ADuM1230

OUTLINE DIMENSIONS

0.10

COMPLIANT TO JEDEC STANDARDS MS-013-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Figure 15. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model

ADuM1230BRWZ1

ADuM1230BRWZ-RL1

No. of Channels 2 2

Output Peak Current (A) 0.1 0.1

Output Voltage (V) 15 15

Temperature Range 40°C to +105°C 40°C to +105°C

Package Description 16-Lead SOIC_W 16-Lead SOIC_W,

13-inch Tape and Reel Option (1, 000 Units)

Package Option RW-16 RW-16

1

Z = Pb-free part.

Rev. A | Page 10 of 12

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ADuM1230

NOTES

Rev. A | Page 11 of 12

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ADuM1230

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

D05460-0-12/05(A)

Rev. A | Page 12 of 12

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