uPD75237GJ-xxx-5BG中文资料

4-BIT SINGLE-CHIP MICROCOMPUTER

μPD75237

MOS INTEGRATED CIRCUIT

The information in this document is subject to change without notice.

? NEC Corporation 1991

Document No.IC-2807A (O. D. No.IC-8009A)Date Published March 1993 P Printed in Japan

The mark 5 shows major revised points.

DESCRIPTION

The μPD75237 is a microcomputer with a CPU capable of 1-, 4-, and 8-bit-wise data processing, a ROM, a RAM,I/O ports, a fluorescent display tube (FIP ?) controller/driver, A/D converters, a watch timer, a timer/pulse generator capable of outputting 14-bit PWM, a serial interface and a vectored interrupt function integrated on a single-chip.

The μPD75237 has the more improved peripheral functions including the RAM capacity, FIP controller/driver display capabilities, I/O ports, A/D converter and serial interface than those of the μPD75217.

The μPD75237 is most suited for advanced and popular VCR timer and tuner applications, single-chip configu-rations of system computers, advanced CD players and advanced microwave ovens.

The μPD75P238 PROM product and various types of development tools (IE-75001-R, assemblers and others) are available for evaluation in system development or small-volume production.

FEATURES

q

Built-in, large-capacity ROM and RAM ?Program memory (ROM): 24K × 8?Data memory (RAM): 1K × 4

q I/O port: 64 ports (except FIP dedicated pins)

q

Minimum instruction execution time: 0.67 μs (when operated at 6.0 MHz)

q

Instruction execution time varying function to achieve a wide range of power supply voltages q

Built-in programmable FIP controller/driver ?Number of segments: 9 to 24?Number of digits: 9 to 16

q 8-bit A/D converter: 8 channels

q Powerful timer/counter function: 5 channels q 8-bit serial interface: 2 channels

q

Interrupt function with importance attached to appli-cations

q

Product with built-in PROM: μPD75P238

ORDERING INFORMATION

Ordering Code

Package

Quality Grade μPD75237GJ-×××-5BG

94-pin plastic QFP (20 × 20 mm)

Standard

Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

LIST OF μPD75237 FUNCTIONS

2

3

AN0 AV REF AV DD V DD V D D X2 X1 IC XT2 XT1 V SS

S16/P100 S17/P101 S18/P102 S19/P103 S20/P110 S21/P111 S22/P112 S23/P113 S0/P120 S1/P121 S2/P122 S3/P123

S 4/P 130S 5/P 131S 6/P 132S 7/P 133S 8/P 140S 9/P 141V L O A D T 15/S 10/P 142T 14/S 11/P 143P H 0/T 13/S 12/P 150P H 1/T 12/S 13/P 151P H 2/T 11/S 14/P 152T 9P H 3/T 10/S 15/P 153T 8T 7T 6T 5T 4T 3T 2T 1T 0V DD V DD

P83/SI1 P82/SO1 P81/SCK1 P80/PPO P73

P72 P71 P70 P63 P62 P61 P60 P53 P52 P51 P50 V SS P43 P42 P41 P40 P33 P32

P 31P 30P 23/B U Z P 22/P C L P 21P 20/P T O 0P 13/T I 0P 12/I N T 2P 11/I N T 1P 10/I N T 0P 03/S I 0/S B 1P 02/S O 0/S B 0P 01/S C K 0P 00/I N T 4R E S E T A N 7/P 93A N 6/P 92A N 5/P 91A N 4/P 90A N 3A N 2A N 1A V S S

PIN CONFIGURATION

Note Be sure to supply power to AV DD , V DD , V SS and AV SS pins (pin Nos. 3, 4, 5, 11, 30, 48, 65 and 87) .

Remarks

Connect the IC (Internally Connected) pin to GND.

5CONTENTS

1.PIN FUNCTIONS (7)

1.1

PORT PINS ...........................................................................................................................................................71.2

NON-PORT PINS..................................................................................................................................................91.3

PIN INPUT/OUPUT CIRCUIT LIST ...................................................................................................................111.4RECOMMENDED CONNECTIONS OF μPD75237 UNUSED PINS (15)

2.μPD75237 ARCHITECTURE AND MEMORY MAP (16)

2.1

DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODE..................................................... 162.2

GENERAL REGISTER BANK CONFIGURATION............................................................................................ 192.3MEMORY MAPPED I/O (22)

3.INTERNAL CPU FUNCTIONS (28)

3.1

PROGRAM COUNTER (PC): 15 BITS.............................................................................................................. 283.2

PROGRAM MEMORY (ROM): 24448 WORDS × 8 BITS ............................................................................... 283.3

DATA MEMORY................................................................................................................................................ 303.4

GENERAL REGISTER: 8 × 4 BITS × 4 BANKS ............................................................................................... 323.5

ACCUMULATOR ............................................................................................................................................... 333.6

STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS)....................................................... 333.7

PROGRAM STATUS WORD (PSW): 8 BITS................................................................................................... 363.8BANK SELECT REGISTER (BS).. (40)

4.PERIPHERAL HARDWARE FUNCTIONS (41)

4.1

DIGITAL INPUT/OUTPUT PORTS................................................................................................................... 414.2

CLOCK GENERATOR........................................................................................................................................ 504.3

CLOCK OUTPUT CIRCUIT................................................................................................................................ 584.4

BASIC INTERVAL TIMER ................................................................................................................................. 614.5

TIMER/EVENT COUNTER................................................................................................................................ 634.6

WATCH TIMER.................................................................................................................................................. 694.7

TIMER/PULSE GENERATOR ........................................................................................................................... 714.8

EVENT COUNTER............................................................................................................................................. 774.9

SERIAL INTERFACE.......................................................................................................................................... 794.10

A/D CONVERTER ........................................................................................................................................... 1134.11

BIT SEQUENTIAL BUFFER: 16 BITS............................................................................................................. 1194.12FIP CONTROLLER/DRIVER. (119)

5.INTERRUPT FUNCTIONS (131)

5.1

INTERRUPT CONTROL CIRCUIT CONFIGURATION................................................................................... 1315.2

INTERRUPT CONTROL CIRCUIT HARDWARE DEVICES ........................................................................... 1335.3

INTERRUPT SEQUENCE ................................................................................................................................ 1385.4

MULTI-INTERRUPT SERVICE CONTROL..................................................................................................... 1395.5VECTOR ADDRESS SHARING INTERRUPT SERVICING (141)

6.STANDBY FUNCTIONS (142)

6.1

STANDBY MODE SETTING AND OPERATING STATE.............................................................................. 1426.2

STANDBY MODE RELEASE .......................................................................................................................... 1446.3OPERATION AFTER STANDBY MODE RELEASE

(146)

657.

RESET FUNCTIONS............................................................................................................................... 1478.INSTRUCTION SET.. (150)

8.1

CHARACTERISTIC INSTRUCTIONS OF μPD75237..................................................................................... 1508.2

INSTRUCTION SET AND OPERATION......................................................................................................... 1538.3OPERATION CODES (162)

9.MASK OPTION SELECTION (168)

10.APPLICATION BLOCK DIAGRAM (169)

11.ELECTRICAL SPECIFICATIONS ........................................................................................................... 17012.CHARACTERISTIC CURVES (REFERENCE VALUES) (183)

13.PACKAGE INFORMATION (185)

14.RECOMMEDED SOLDERING CONDITIONS....................................................................................... 186APPENDIX A.

LIST OF μPD75238 SERIES PRODUCT FUNCTIONS..................................................... 187APPENDIX B.DEVELOPMENT TOOLS (188)

7

1.PIN FUNCTIONS

1.1

PORT PINS (1/2)

P00P01P02P03P10P11P12P13P20P21P22P23P30P31P32P33P40 to P43

P50 to P53

P60P61

P62P63P70P71P72P73

Pin Name I/O

After Reset Input/output

*24-bit input port (PORT0).

Built-in pull-up resistor can be specified in 3-bit units by software for P01 to P03.

4-bit input port (PORT1).

Built-in pull-up resistor can be specified in 4-bit units by software.

Noise removing function available

4-bit input/ output port (PORT2).

Built-in pull-up resistor can be specified in 4-bit units by software.

×

×

B

F – A F – B M – C

B – C

E – B

×

Input

Input

Input Input

Input Input/output

Programmable 4-bit input/ output port (PORT3).Input/ output specifiable in 1-bit units.

Built-in pull-up resistor can be specified in 4-bit units by software.

Input/output

Input/output

N-ch open-drain 4-bit input/output port (PORT4).Pull-up resistor can be incorporated in 1-bit units (mask option).

10 V withstand voltage with open drain.

N-ch open-drain 4-bit input/ output port (PORT5).Pull-up resistor can be incorporated in 1-bit units (mask option).

10 V withstand voltage with open drain.

q

Input E – C

×

M

M

Function

Dual-Function Pin

*2 *2 *2

*2

*2

q

Input/output

Input/output 4-bit input/output port (PORT7).

Built-in pull-down resistor can be incorporated in 1-bit units (mask option).

INT4

SCK0SO0/SB0SI0/SB1INT0

INT1INT2TI0PTO0

—PCL BUZ —

———

—

—

————————

Input

V SS level

(when a pull-down resistor is incorpo-rated) or high impedance

E – C

V

Programmable 4-bit input/output port (PORT6).Input/output specifiable in 1-bit units.

Built -in pull-up resistor can be specified in 4-bit units by software.

Input / Output Circuit Type *18-Bit

I/O

* 1.Schmitt trigger inputs are circled.2.Can drive LED directly.

High level (when a pull-up resistor is incorporated)or high im-pedance High level (when a pull-up resistor is incorporated)or high im-pedance

8

Pin Name

I/O Function

Dual-Function Pin

After Reset Input/output Input/output Input/output 4-bit input port (PORT9).

P-ch open-drain 4-bit high-voltage output port.Pull-down resistor can be incorporated (mask op-tion).

P-ch open-drain 4-bit high-voltage output port.Pull-down resistor can be incorporated (mask op-

tion).

A

F

E B

×

Input Y – A

q

I – F

P-ch open-drain 4-bit high-voltage output port.Pull-down resistor can be incorporated (mask op-tion).

P-ch open-drain 4-bit high-voltage output port.Pull-down resistor can be incorporated (mask op-tion).

q

P80

P81P82P83P90P91P92P93P100P101P102P103P110P111P112P113P120P121P122P123P130P131P132P133P140P141P142P143P150P151P152P153PH0PH1PH2PH3

P-ch open-drain 4-bit high-voltage output port.Pull-down resistor can be incorporated (mask op-tion).

P142 and P143 can drive LED directly.

Input

PPO

SCK1

SO1SI1AN4

AN5AN6AN7S16

S17S18S19S20

S21S22S23S0

S1S2S3S4

S5S6S7S8

S9S10/T15S11/T14S12/T13/PH0

S13/T12/PH1S14/T11/PH2S15/T10/PH3S12/T13/P150

S13/T12/P151S14/T11/P152S15/T10/P153

Input

Output

Output

Output

Output

Output

Output

Output

P-ch open-drain 4-bit high-voltage output port.Pull-down resistor can be incorporated (mask op-tion).

q

×

1.1PORT PINS (2/2)

*Schmitt trigger inputs are circled.

V LOAD level (when a pull-down resistor to V LOAD is in-corporated) or high imped-ance

I – C

P-ch open-drain 4-bit high-voltage output port.Pull-down resistor can be incorporated (mask op-tion).

These ports can drive LED directly.

Input / Output Circuit Type *

×

4-bit input port (PORT8).

Input

V LOAD level (when a pull-down resistor to V LOAD is in-corporated),V SS level (when a pull-down resistor to V SS is incor-porated) or high imped-ance

8-Bit

I/O

9

1.2NON-PORT PINS (1/2)

Pin Name I/O

Dual-Function Pin

Input / Output Circuit Type *

T0 to T9

T10/S15 to T13/S12

T14/S11T15/S10S0 to S3

S4 to S7S8S9

S16 to S19

S20 to S23

TI0PTO0PCL BUZ

SCK0SO0/SB0SI0/SB1After Reset

Output

I – C

I – F

V LOAD level (when a pull-down resistor to V LOAD is in-c o r p o -rated), V SS level (when a pull-down resistor to V SS is incor-porated) or high im-pedance

Segment high-voltage output pins.

These pins can be used as PORT10 and PORT11 in the static mode.

—

PH3/P153 to PH0/P150

P143

P142P120 to P123

P130 to P133P140P141

P100 to P103

P110 to

P113

P13P20P22P23

P01P02P03FIP controller/driver out-put pins.

Pull-down resistor can

be incorporated in bit

units (mask option).

Digit/segment output dual-func-tion high-voltage high-current output pins. Extra pins can be used as PORTH. These pins can be used as PORT15 in the static mode.

Digit output high-voltage high-current output pins.

Digit/segment output dual-func-tion high-voltage high-current output pins. These pins can be used as POTR14 in the static mode.

Clock output.

Fixed frequency output (for buzzer or system clock trim-ming).

Input/output Input/output Serial clock input/output.Serial data output.

Serial bus input/output.Input/output

Serial data input.

Serial bus input/output.

Timer/event counter output.Output Output External event pulse input to timer/event counter #0 and event counter #1.

—Input Input Input

Input

Input

Input

Input B – C E – B E – B E – B

F – A

F – B

M – C

*Schmitt trigger inputs are circled.

Output Segment high-voltage output

pins.

These pins can be used as

PORT12 to PORT14 in the static mode.

V LOAD level (when a pull-down resistor to V LOAD is in-c o r p o -rated) or high im-pedance.

Function

10

1.2NON-PORT PINS (2/2)

Input

Edge-detected testable input (rising edge detection).

Input

Input/output Output Serial data output. B – C

—

—Input —

Input Input —Input Output

———

Serial data input.

Input Analog input to A/D converter.A/D converter power supply.

A/D converter reference voltage input.A/D converter reference GND potential.

Subsystem clock oscillation crystal connection. An exter-nal clock is input to XT1 and XT2 is made open.System reset input.

Timer/pulse generator pulse output.—GND potential.

Positive power supply.FIP controller/driver pull-down resistor connect/power supply.

Input Dual-Function Pin

Pin Name I/O

After Reset

Input / Output Circuit Type *

*Schmitt trigger inputs are circled.

Edge-detected vectored interrupt input (valid for detec-tion of rising and falling edges).

Clocked

Asynchronous

Asynchronous Serial clock input/output.Main system clock oscillation crystal/ceramic connec-tion. An external clock is input to X1 and an antiphase clock is input to X2.

Function

INT4INT0

INT1

INT2

SCK1SO1SI1AN0 to AN3AN4 to AN7

AV DD AV REF AV SS

X1, X2XT1XT2RESET PPO V DD (3 – Pin)V SS (2 – Pin)

V LOAD

P00P10

P11

P12

P81P82P83—P90 to P93

———

—

—P80———

Input Edge-detected vectored interrupt in-put (detected edge selection possible).

——Input Input Input ————

———Input ———

B

B – C

F E B Y Y – A —Z —

—

—B ————

11

1.3PIN INPUT/OUTPUT CIRCUIT LIST (1/4)

12

1.3PIN INPUT/OUTPUT CIRCUIT LIST (2/4)

13

1.3PIN INPUT/OUTPUT CIRCUIT LIST (3/4)

141.3PIN INPUT/OUTPUT CIRCUIT LIST (4/4)

151.4RECOMMENDED CONNECTIONS OF μPD75237 UNUSED PINS P00/INT4P01/SCK0P02/SO0/SB0

P03/SI1/SB1

P10/INT0 to P12/INT2

P13/TI0

P20/PTO0

P21

P22/PCL

P23/BUZ

P30 to P33

P40 to P43

P50 to P53

P60 to P63

P70 to P73

P80/PPO

P81/SCK1

P82/SO1

P83/SI1

P90/AN4 to P93/AN7

P100/S16 to P103/S19

P110/S20 to P113/S23

P120 to P123

P130 to P133

P140 to P143

P150 to P153

AN0 to AN3

AV REF

AV DD

AV SS

XT1

XT2

V LOAD Pin Connect to V SS Connect to V SS or V DD Input state : Connect to V SS or V DD Ouput state : Leave open Connect to V SS Connect to V DD Connect to V SS Connect to V SS or V DD Leave open Connect to V SS

Recommended Connection

Connect to V SS Leave open Connect to V SS

162.μPD75237 ARCHITECTURE AND MEMORY MAP

The μPD75237 has the following three architectural features.

(a)

Data memory bank configuration (b)

General register bank configuration (c)Memory mapped I/O

Each feature is outlined below.

2.1DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODE

As shown in Fig. 2-1, the μPD75237 incorporates a static RAM (928 words × 4 bits) at addresses 000H to 19FH and 200H to 3FFH in the data memory space and a display data memory (96 words × 4 bits) at addresses 1A0H to 1FFH and peripheral hardware (input/output ports, timers, etc.) at addresses F80H to FFFH. For addressing of this 12-bit address data memory space, the memory bank has a configuration wherein the lower 8 bits are directly or indirectly specified by an instruction and the higher 4-bit address is specified by a memory bank (MB).

A memory bank enable flag (MBE) and a memory bank select register (MBS) are incorporated to specify the memory bank (MB) and addressing operations shown in Fig. 2-1 and Table 2-1 can be carried out. (MBS is a register to select the memory bank and can set 0, 1, 2, 3 and 15. MBE is a flag to determine whether the memory bank selected by MBS should be validated or not. Since MBE is automatically saved/reset for interrupt or subroutine processing,it can be freely set for either processing.)

For data memory space addressing, set MBE = 1 normally and manipulate the memory bank static RAM specified by MBS. Efficient programming is possible by using the MBE = 0 or MBE = 1 mode for each program processing.Applicable Program Processing Interrupt service

MBE = 0 mode Processing of repeating built-in hardware manipulation and static RAM manipulation

Subroutine processing

MBE = 1 mode

Normal program processing

17

Fig. 2-1 Date Memory Configuration and Addressing Range in Each Addressing Mode

Remarks —:Don’t care

01FH 020H 000H 07FH

0FFH 100H

19FH 1A0H 1FFH 200H

3FFH

2FFH 300H

FFFH

FC0H

F80H

18Table 2-1 Addressing Modes

As described in Table 2-1, direct and indirect addressing is possible for each of 1-bit, 4-bit and 8-bit data in μPD75237 data memory manipulation. Thus, easy-to-understand programs can be created very efficiently.

192.2GENERAL REGISTER BANK CONFIGURATION

The μPD75237 incorporates four register banks, each bank consisting of eight general registers, X, A, B, C, D,E, H and L. This general register area is mapped at addresses 00H to 1FH of the memory bank 0 of the data memory (refer to Fig. 2-2 General Register Configuration (4-Bit Processing)). A register bank enable flag (RBE) and a register bank select register (RBS) are incorporated to specify the above general register banks. RBS is a register to select a register bank and RBE is a flag to determine whether the register bank selected by RBS should be validated or not. The register bank (RB) which is validated for instruction execution is given as

RB = RBE? RBS.

As described above, with the μPD75237 having four register banks, programs can be created very efficiently by using different register banks for normal processing and interrupt service as described in Table 2-2. (RBE is automatically saved and set for interrupt service and automatically reset upon termination of the interrupt service.)

Table 2-2 Recommended Use of Register Banks in Normal and Interrupt Routines Normal processing

Use register banks 2 and 3 with RBE = 1.Single interrupt service

Use register bank 0 with RBE = 0.Double interrupt service

Use register bank 1 with RBE = 1. (It is necessary to save/reset RBS.)Triple or more interrupt service Save/reset registers by PUSH and POP.Not only in 4-bit units, a register pair of XA, HL, DE or BC can transfer, compare, operate, increment or decrement

data in 8-bit units. In this case, register pairs with the reversed bit 0 of the register bank specified by RBE?RBS can be specified as XA’, HL’, DE’ and BC’. Thus, the μPD75237 has eight 8-bit registers (refer to Fig. 2-3 General Register Configuration (8-Bit Processing)).

20

Fig. 2-2 General Register Configuration (4-Bit Processing)

21

Fig. 2-3 General Register Configuration (8-Bit Processing)

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