msp430g2553.h文档

/********************************************************************

* Standard register and bit definitions for the Texas Instruments * MSP430 microcontroller.

* This file supports assembler and C development for * MSP430G2553 devices.

* Texas Instruments, Version 1.0 * Rev. 1.0, Setup

********************************************************************/

#ifndef __MSP430G2553 #define __MSP430G2553

#define __MSP430_HEADER_VERSION__ 1062 #ifdef __cplusplus extern \ { #endif

/*----------------------------------------------------------------------------*/

/* PERIPHERAL FILE MAP /*----------------------------------------------------------------------------*/ /* External references resolved by a device-specific linker command file */

#define SFR_8BIT(address) extern volatile unsigned char address #define SFR_16BIT(address) extern volatile unsigned int address /************************************************************ * STANDARD BITS

************************************************************/

#define BIT0 (0x0001) #define BIT1 (0x0002) #define BIT2 (0x0004) #define BIT3 (0x0008) #define BIT4 (0x0010) #define BIT5 (0x0020) #define BIT6 (0x0040) #define BIT7 (0x0080) #define BIT8 (0x0100) #define BIT9 (0x0200) #define BITA (0x0400) #define BITB (0x0800)

#define BITC (0x1000) #define BITD (0x2000) #define BITE (0x4000) #define BITF (0x8000)

/************************************************************ * STATUS REGISTER BITS

************************************************************/ #define C (0x0001) #define Z (0x0002) #define N (0x0004) #define V (0x0100) #define GIE (0x0008) #define CPUOFF (0x0010) #define OSCOFF (0x0020) #define SCG0 (0x0040) #define SCG1 (0x0080)

/* Low Power Modes coded with Bits 4-7 in SR */

#ifdef __ASM_HEADER__ /* Begin #defines for assembler */ #define LPM0 (CPUOFF)

#define LPM1 (SCG0+CPUOFF) #define LPM2 (SCG1+CPUOFF)

#define LPM3 (SCG1+SCG0+CPUOFF)

#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) /* End #defines for assembler */

#else /* Begin #defines for C */

#define LPM0_bits (CPUOFF)

#define LPM1_bits (SCG0+CPUOFF) #define LPM2_bits (SCG1+CPUOFF)

#define LPM3_bits (SCG1+SCG0+CPUOFF)

#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)

#include \

#define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */

#define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */

#define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */

#define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */

#define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */

#define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */

#define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */

#define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */

#define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */

#define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */

#endif /* End #defines for C */

/************************************************************ * PERIPHERAL FILE MAP

************************************************************/

/************************************************************ * SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS

************************************************************/

SFR_8BIT(IE1); /* Interrupt Enable 1 */

#define WDTIE (0x01) /* Watchdog Interrupt Enable */

#define OFIE (0x02) /* Osc. Fault Interrupt Enable */

#define NMIIE (0x10) /* NMI Interrupt Enable */

#define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */

SFR_8BIT(IFG1); /* Interrupt Flag 1 */

#define WDTIFG (0x01) /* Watchdog Interrupt Flag */

#define OFIFG (0x02) /* Osc. Fault Interrupt Flag */ #define PORIFG (0x04) /* Power On Interrupt Flag */

#define RSTIFG (0x08) /* Reset Interrupt Flag */ #define NMIIFG (0x10) /* NMI Interrupt Flag

*/

SFR_8BIT(IE2); /* Interrupt Enable 2 */

#define UC0IE IE2 #define UCA0RXIE (0x01) #define UCA0TXIE (0x02) #define UCB0RXIE (0x04) #define UCB0TXIE (0x08)

SFR_8BIT(IFG2); /* Interrupt Flag 2 */

#define UC0IFG IFG2 #define UCA0RXIFG (0x01) #define UCA0TXIFG (0x02) #define UCB0RXIFG (0x04) #define UCB0TXIFG (0x08)

/************************************************************ * ADC10

************************************************************/ #define __MSP430_HAS_ADC10__ /* Definition to show that Module is available */

SFR_8BIT(ADC10DTC0); /* ADC10 Data Transfer Control 0 */

SFR_8BIT(ADC10DTC1); /* ADC10 Data Transfer Control 1 */

SFR_8BIT(ADC10AE0); /* ADC10 Analog Enable 0 */

SFR_16BIT(ADC10CTL0); /* ADC10 Control 0 */ SFR_16BIT(ADC10CTL1); /* ADC10 Control 1 */ SFR_16BIT(ADC10MEM); /* ADC10 Memory */ SFR_16BIT(ADC10SA); /* ADC10 Data Transfer Start Address */

/* ADC10CTL0 */

#define ADC10SC (0x001) /* ADC10 Start Conversion */

#define ENC (0x002) /* ADC10 Enable Conversion */

#define ADC10IFG (0x004) /* ADC10 Interrupt Flag */

#define ADC10IE (0x008) /* ADC10 Interrupt Enalbe */ #define ADC10ON (0x010) /* ADC10 On/Enable */ #define REFON (0x020) /* ADC10 Reference on */

#define REF2_5V (0x040) /* ADC10 Ref 0:1.5V / 1:2.5V */

#define MSC (0x080) /* ADC10 Multiple SampleConversion */

#define REFBURST (0x100) Burst Mode */

#define REFOUT (0x200) output of Ref. */

#define ADC10SR (0x400) Rate 0:200ksps / 1:50ksps */

#define ADC10SHT0 (0x800) Select Bit: 0 */

#define ADC10SHT1 (0x1000) Select Bit: 1 */

#define SREF0 (0x2000) Select Bit: 0 */

#define SREF1 (0x4000) Select Bit: 1 */

#define SREF2 (0x8000) Select Bit: 2 */

#define ADC10SHT_0 (0*0x800u) #define ADC10SHT_1 (1*0x800u) #define ADC10SHT_2 (2*0x800u) #define ADC10SHT_3 (3*0x800u)

#define SREF_0 (0*0x2000u) = AVSS */ #define SREF_1 (1*0x2000u) = AVSS */

#define SREF_2 (2*0x2000u) VR- = AVSS */

#define SREF_3 (3*0x2000u) VR- = AVSS */

#define SREF_4 (4*0x2000u) = VREF-/VEREF- */ #define SREF_5 (5*0x2000u) = VREF-/VEREF- */

#define SREF_6 (6*0x2000u) VR- = VREF-/VEREF- */

/* ADC10 Reference /* ADC10 Enalbe /* ADC10 Sampling /* ADC10 Sample Hold /* ADC10 Sample Hold /* ADC10 Reference /* ADC10 Reference /* ADC10 Reference /* 4 x ADC10CLKs */ /* 8 x ADC10CLKs */ /* 16 x ADC10CLKs */ /* 64 x ADC10CLKs */ /* VR+ = AVCC and VR- /* VR+ = VREF+ and VR- /* VR+ = VEREF+ and /* VR+ = VEREF+ and /* VR+ = AVCC and VR- /* VR+ = VREF+ and VR- /* VR+ = VEREF+ and

#define SREF_7 (7*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */

/* ADC10CTL1 */

#define ADC10BUSY (0x0001) /* ADC10 BUSY */ #define CONSEQ0 (0x0002) /* ADC10 Conversion Sequence Select 0 */

#define CONSEQ1 (0x0004) /* ADC10 Conversion Sequence Select 1 */

#define ADC10SSEL0 (0x0008) Source Select Bit: 0 */

#define ADC10SSEL1 (0x0010) Source Select Bit: 1 */

#define ADC10DIV0 (0x0020) Divider Select Bit: 0 */

#define ADC10DIV1 (0x0040) Divider Select Bit: 1 */

#define ADC10DIV2 (0x0080) Divider Select Bit: 2 */

#define ISSH (0x0100) Sample Hold Signal */

#define ADC10DF (0x0200) 0:binary 1:2's complement */

#define SHS0 (0x0400) Source Bit: 0 */

#define SHS1 (0x0800) Source Bit: 1 */

#define INCH0 (0x1000) Channel Select Bit: 0 */

#define INCH1 (0x2000) Channel Select Bit: 1 */

#define INCH2 (0x4000) Channel Select Bit: 2 */

#define INCH3 (0x8000) Channel Select Bit: 3 */

#define CONSEQ_0 (0*2u) single conversion */

#define CONSEQ_1 (1*2u) channels */

#define CONSEQ_2 (2*2u) channel */ #define CONSEQ_3 (3*2u) channels */

/* ADC10 Clock /* ADC10 Clock /* ADC10 Clock /* ADC10 Clock /* ADC10 Clock /* ADC10 Invert /* ADC10 Data Format /* ADC10 Sample/Hold /* ADC10 Sample/Hold /* ADC10 Input /* ADC10 Input /* ADC10 Input /* ADC10 Input /* Single channel /* Sequence of /* Repeat single /* Repeat sequence of

#define ADC10SSEL_0 (0*8u) /* ADC10OSC */ #define ADC10SSEL_1 (1*8u) /* ACLK */ #define ADC10SSEL_2 (2*8u) /* MCLK */ #define ADC10SSEL_3 (3*8u) /* SMCLK */

#define ADC10DIV_0 (0*0x20u) /* ADC10 Clock Divider Select 0 */

#define ADC10DIV_1 (1*0x20u) /* ADC10 Clock Divider Select 1 */

#define ADC10DIV_2 (2*0x20u) Divider Select 2 */

#define ADC10DIV_3 (3*0x20u) Divider Select 3 */

#define ADC10DIV_4 (4*0x20u) Divider Select 4 */

#define ADC10DIV_5 (5*0x20u) Divider Select 5 */

#define ADC10DIV_6 (6*0x20u) Divider Select 6 */

#define ADC10DIV_7 (7*0x20u) Divider Select 7 */

#define SHS_0 (0*0x400u) #define SHS_1 (1*0x400u) #define SHS_2 (2*0x400u) #define SHS_3 (3*0x400u)

#define INCH_0 (0*0x1000u) */

#define INCH_1 (1*0x1000u) */

#define INCH_2 (2*0x1000u) */

#define INCH_3 (3*0x1000u) */

#define INCH_4 (4*0x1000u) */

#define INCH_5 (5*0x1000u) */

#define INCH_6 (6*0x1000u) */

#define INCH_7 (7*0x1000u) */

/* ADC10 Clock /* ADC10 Clock /* ADC10 Clock /* ADC10 Clock /* ADC10 Clock /* ADC10 Clock /* ADC10SC */ /* TA3 OUT1 */ /* TA3 OUT0 */ /* TA3 OUT2 */ /* Selects Channel 0 /* Selects Channel 1 /* Selects Channel 2 /* Selects Channel 3 /* Selects Channel 4 /* Selects Channel 5 /* Selects Channel 6 /* Selects Channel 7 #define INCH_8 (8*0x1000u) /* Selects Channel 8 */

#define INCH_9 (9*0x1000u) /* Selects Channel 9 */

#define INCH_10 (10*0x1000u) /* Selects Channel 10 */

#define INCH_11 (11*0x1000u) /* Selects Channel 11 */

#define INCH_12 (12*0x1000u) /* Selects Channel 12 */

#define INCH_13 (13*0x1000u) /* Selects Channel 13 */

#define INCH_14 (14*0x1000u) /* Selects Channel 14 */

#define INCH_15 (15*0x1000u) /* Selects Channel 15 */

/* ADC10DTC0 */

#define ADC10FETCH (0x001) /* This bit should normally be reset */ #define ADC10B1 (0x002) /* ADC10 block one */ #define ADC10CT (0x004) /* ADC10 continuous transfer */

#define ADC10TB (0x008) /* ADC10 two-block mode */

#define ADC10DISABLE (0x000) /* ADC10DTC1 */

/************************************************************ * Basic Clock Module

************************************************************/ #define __MSP430_HAS_BC2__ /* Definition to show that Module is available */

SFR_8BIT(DCOCTL); /* DCO Clock Frequency Control */

SFR_8BIT(BCSCTL1); /* Basic Clock System Control 1 */

SFR_8BIT(BCSCTL2); /* Basic Clock System Control 2 */

SFR_8BIT(BCSCTL3); /* Basic Clock System Control 3 */

#define MOD0 (0x01) /* Modulation Bit 0 */ #define MOD1 (0x02) /* Modulation Bit 1 */

#define MOD2 (0x04) /* Modulation Bit 2 */ #define MOD3 (0x08) /* Modulation Bit 3 */ #define MOD4 (0x10) /* Modulation Bit 4 */ #define DCO0 (0x20) /* DCO Select Bit 0 */ #define DCO1 (0x40) /* DCO Select Bit 1 */ #define DCO2 (0x80) /* DCO Select Bit 2 */

#define RSEL0 (0x01) /* Range Select Bit 0 */

#define RSEL1 (0x02) */

#define RSEL2 (0x04) */

#define RSEL3 (0x08) */

#define DIVA0 (0x10) #define DIVA1 (0x20) #define XTS (0x40) / 1: High Freq. */

#define XT2OFF (0x80)

#define DIVA_0 (0x00) */

#define DIVA_1 (0x10) */

#define DIVA_2 (0x20) */

#define DIVA_3 (0x30) */

#define DIVS0 (0x02) #define DIVS1 (0x04) #define SELS (0x08) Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */#define DIVM0 (0x10) #define DIVM1 (0x20) #define SELM0 (0x40) 0 */ #define SELM1 (0x80) 1 */

#define DIVS_0 (0x00) */

#define DIVS_1 (0x02) /* Range Select Bit 1 /* Range Select Bit 2 /* Range Select Bit 3 /* ACLK Divider 0 */ /* ACLK Divider 1 */ /* LFXTCLK 0:Low Freq. /* Enable XT2CLK */ /* ACLK Divider 0: /1 /* ACLK Divider 1: /2 /* ACLK Divider 2: /4 /* ACLK Divider 3: /8 /* SMCLK Divider 0 */ /* SMCLK Divider 1 */ /* SMCLK Source /* MCLK Divider 0 */ /* MCLK Divider 1 */ /* MCLK Source Select /* MCLK Source Select /* SMCLK Divider 0: /1 /* SMCLK Divider 1: /2

*/

#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */

#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */

#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */

#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */

#define DIVM_2 (0x20) */

#define DIVM_3 (0x30) */

#define SELM_0 (0x00) 0: DCOCLK */ #define SELM_1 (0x40) 1: DCOCLK */ #define SELM_2 (0x80) 2: XT2CLK/LFXTCLK */ #define SELM_3 (0xC0) 3: LFXTCLK */

#define LFXT1OF (0x01) Frequency Oscillator Fault Flag */

#define XT2OF (0x02) oscillator 2 fault flag */

#define XCAP0 (0x04) #define XCAP1 (0x08) #define LFXT1S0 (0x10) (XTS = 0) */

#define LFXT1S1 (0x20) (XTS = 0) */

#define XT2S0 (0x40) #define XT2S1 (0x80)

#define XCAP_0 (0x00) */

#define XCAP_1 (0x04) */

#define XCAP_2 (0x08) pF */ #define XCAP_3 (0x0C) /* MCLK Divider 2: /4 /* MCLK Divider 3: /8 /* MCLK Source Select /* MCLK Source Select /* MCLK Source Select /* MCLK Source Select /* Low/high /* High frequency /* XIN/XOUT Cap 0 */ /* XIN/XOUT Cap 1 */ /* Mode 0 for LFXT1 /* Mode 1 for LFXT1 /* Mode 0 for XT2 */ /* Mode 1 for XT2 */ /* XIN/XOUT Cap : 0 pF /* XIN/XOUT Cap : 6 pF /* XIN/XOUT Cap : 10 /* XIN/XOUT Cap : 12.5

pF */

#define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */

#define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */

#define LFXT1S_2 (0x20) /* Mode 2 for LFXT1 : VLO */

#define LFXT1S_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */

#define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */

#define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */

#define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */

#define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal */

/************************************************************ * Comparator A

************************************************************/ #define __MSP430_HAS_CAPLUS__ /* Definition to show that Module is available */

SFR_8BIT(CACTL1); /* Comparator A Control 1 */

SFR_8BIT(CACTL2); /* Comparator A Control 2 */

SFR_8BIT(CAPD); /* Comparator A Port Disable */

#define CAIFG (0x01) /* Comp. A Interrupt Flag */

#define CAIE (0x02) /* Comp. A Interrupt Enable */

#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */

#define CAON (0x08) /* Comp. A enable */ #define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */

#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */

#define CARSEL (0x40) /* Comp. A Internal Reference Enable */

#define CAEX (0x80) /* Comp. A Exchange Inputs */

#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */

#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */

#define CAREF_2 (0x20) Select 2 : 0.5*Vcc */

#define CAREF_3 (0x30) Select 3 : Vt*/

#define CAOUT (0x01) #define CAF (0x02) Output Filter */

#define P2CA0 (0x04) Multiplexer */

#define P2CA1 (0x08) Multiplexer */

#define P2CA2 (0x10) Multiplexer */

#define P2CA3 (0x20) Multiplexer */

#define P2CA4 (0x40) Multiplexer */ #define CASHORT (0x80) - Terminals */

#define CAPD0 (0x01) Input Buffer of Port Register .0 */

#define CAPD1 (0x02) Input Buffer of Port Register .1 */

#define CAPD2 (0x04) Input Buffer of Port Register .2 */

#define CAPD3 (0x08) Input Buffer of Port Register .3 */

#define CAPD4 (0x10) Input Buffer of Port Register .4 */

#define CAPD5 (0x20) Input Buffer of Port Register .5 */

#define CAPD6 (0x40) Input Buffer of Port Register .6 */

/* Comp. A Int. Ref. /* Comp. A Int. Ref. /* Comp. A Output */ /* Comp. A Enable /* Comp. A +Terminal /* Comp. A -Terminal /* Comp. A -Terminal /* Comp. A -Terminal /* Comp. A +Terminal /* Comp. A Short + and /* Comp. A Disable /* Comp. A Disable /* Comp. A Disable /* Comp. A Disable /* Comp. A Disable /* Comp. A Disable /* Comp. A Disable #define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */

/************************************************************* * Flash Memory

*************************************************************/ #define __MSP430_HAS_FLASH2__ /* Definition to show that Module is available */

SFR_16BIT(FCTL1); /* FLASH Control 1 */ SFR_16BIT(FCTL2); /* FLASH Control 2 */ SFR_16BIT(FCTL3); /* FLASH Control 3 */

#define FRKEY (0x9600) /* Flash key returned by read */

#define FWKEY (0xA500) /* Flash key for write */

#define FXKEY (0x3300) /* for use with XOR instruction */

#define ERASE (0x0002) /* Enable bit for Flash segment erase */

#define MERAS (0x0004) /* Enable bit for Flash mass erase */

#define WRT (0x0040) /* Enable bit for Flash write */

#define BLKWRT (0x0080) /* Enable bit for Flash segment write */

#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */

#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */

#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */ #ifndef FN2

#define FN2 (0x0004) #endif

#ifndef FN3

#define FN3 (0x0008) #endif

#ifndef FN4

#define FN4 (0x0010) #endif

#define FN5 (0x0020) #define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */ #define FSSEL1 (0x0080) /* Flash clock select 1 */

#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */ #define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */ #define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */ #define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */

#define BUSY (0x0001) /* Flash busy: 1 */ #define KEYV (0x0002) /* Flash Key violation flag */

#define ACCVIFG (0x0004) /* Flash Access violation flag */

#define WAIT (0x0008) /* Wait flag for segment write */ #define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */

#define EMEX (0x0020) /* Flash Emergency Exit */

#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */

#define FAIL (0x0080) /* Last Program or Erase failed */

/************************************************************ * DIGITAL I/O Port1/2 Pull up / Pull down Resistors

************************************************************/ #define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */

#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */

SFR_8BIT(P1IN); /* Port 1 Input */ SFR_8BIT(P1OUT); /* Port 1 Output */ SFR_8BIT(P1DIR); /* Port 1 Direction */

SFR_8BIT(P1IFG); /* Port 1 Interrupt

Flag */

SFR_8BIT(P1IES); /* Port 1 Interrupt Edge Select */

SFR_8BIT(P1IE); /* Port 1 Interrupt Enable */

SFR_8BIT(P1SEL); /* Port 1 Selection */

SFR_8BIT(P1SEL2); /* Port 1 Selection 2 */

SFR_8BIT(P1REN); /* Port 1 Resistor Enable */

SFR_8BIT(P2IN); /* Port 2 Input */ SFR_8BIT(P2OUT); /* Port 2 Output */ SFR_8BIT(P2DIR); /* Port 2 Direction */

SFR_8BIT(P2IFG); /* Port 2 Interrupt Flag */

SFR_8BIT(P2IES); /* Port 2 Interrupt Edge Select */

SFR_8BIT(P2IE); /* Port 2 Interrupt Enable */

SFR_8BIT(P2SEL); /* Port 2 Selection */

SFR_8BIT(P2SEL2); /* Port 2 Selection 2 */

SFR_8BIT(P2REN); /* Port 2 Resistor Enable */

/************************************************************ * DIGITAL I/O Port3 Pull up / Pull down Resistors

************************************************************/ #define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */

SFR_8BIT(P3IN); /* Port 3 Input */ SFR_8BIT(P3OUT); /* Port 3 Output */ SFR_8BIT(P3DIR); /* Port 3 Direction */

SFR_8BIT(P3SEL); /* Port 3 Selection */

SFR_8BIT(P3SEL2); /* Port 3 Selection 2 */

SFR_8BIT(P3REN); /* Port 3 Resistor

Enable */

/************************************************************ * Timer0_A3

************************************************************/ #define __MSP430_HAS_TA3__ /* Definition to show that Module is available */

SFR_16BIT(TA0IV); /* Timer0_A3 Interrupt Vector Word */

SFR_16BIT(TA0CTL); */

SFR_16BIT(TA0CCTL0); Capture/Compare Control 0 */

SFR_16BIT(TA0CCTL1); Capture/Compare Control 1 */

SFR_16BIT(TA0CCTL2); Capture/Compare Control 2 */

SFR_16BIT(TA0R); SFR_16BIT(TA0CCR0); Capture/Compare 0 */

SFR_16BIT(TA0CCR1); Capture/Compare 1 */

SFR_16BIT(TA0CCR2); Capture/Compare 2 */

/* Alternate register names */

#define TAIV TA0IV Vector Word */

#define TACTL TA0CTL #define TACCTL0 TA0CCTL0 Capture/Compare Control 0 */

#define TACCTL1 TA0CCTL1 Capture/Compare Control 1 */

#define TACCTL2 TA0CCTL2 Capture/Compare Control 2 */

#define TAR TA0R #define TACCR0 TA0CCR0 Capture/Compare 0 */

#define TACCR1 TA0CCR1 Capture/Compare 1 */

#define TACCR2 TA0CCR2 Capture/Compare 2 */

#define TAIV_ TA0IV_ /* Timer0_A3 Control /* Timer0_A3 /* Timer0_A3 /* Timer0_A3 /* Timer0_A3 */ /* Timer0_A3 /* Timer0_A3 /* Timer0_A3 /* Timer A Interrupt /* Timer A Control *//* Timer A /* Timer A /* Timer A /* Timer A */ /* Timer A /* Timer A /* Timer A /* Timer A Interrupt

Vector Word */

#define TACTL_ TA0CTL_ /* Timer A Control */ #define TACCTL0_ TA0CCTL0_ /* Timer A Capture/Compare Control 0 */

#define TACCTL1_ TA0CCTL1_ /* Timer A Capture/Compare Control 1 */

#define TACCTL2_ TA0CCTL2_ /* Timer A Capture/Compare Control 2 */

#define TAR_ TA0R_ /* Timer A */ #define TACCR0_ TA0CCR0_ Capture/Compare 0 */

#define TACCR1_ TA0CCR1_ Capture/Compare 1 */

#define TACCR2_ TA0CCR2_ Capture/Compare 2 */

/* Alternate register names 2 */

#define CCTL0 TACCTL0 Capture/Compare Control 0 */

#define CCTL1 TACCTL1 Capture/Compare Control 1 */

#define CCTL2 TACCTL2 Capture/Compare Control 2 */

#define CCR0 TACCR0 Capture/Compare 0 */

#define CCR1 TACCR1 Capture/Compare 1 */

#define CCR2 TACCR2 Capture/Compare 2 */

#define CCTL0_ TACCTL0_ Capture/Compare Control 0 */

#define CCTL1_ TACCTL1_ Capture/Compare Control 1 */

#define CCTL2_ TACCTL2_ Capture/Compare Control 2 */

#define CCR0_ TACCR0_ Capture/Compare 0 */

#define CCR1_ TACCR1_ Capture/Compare 1 */

#define CCR2_ TACCR2_ Capture/Compare 2 */

#define TASSEL1 (0x0200) source select 1 */

/* Timer A /* Timer A /* Timer A /* Timer A /* Timer A /* Timer A /* Timer A /* Timer A /* Timer A /* Timer A /* Timer A /* Timer A /* Timer A /* Timer A /* Timer A /* Timer A clock #define TASSEL0 (0x0100) /* Timer A clock source select 0 */ #define ID1 (0x0080) /* Timer A clock input divider 1 */ #define ID0 (0x0040) /* Timer A clock input divider 0 */

#define MC1 (0x0020) /* Timer A mode control 1 */

#define MC0 (0x0010) /* Timer A mode control 0 */

#define TACLR (0x0004) clear */

#define TAIE (0x0002) interrupt enable */

#define TAIFG (0x0001) interrupt flag */

#define MC_0 (0*0x10u) control: 0 - Stop */

#define MC_1 (1*0x10u) control: 1 - Up to CCR0 */

#define MC_2 (2*0x10u) control: 2 - Continous up */

#define MC_3 (3*0x10u) control: 3 - Up/Down */

#define ID_0 (0*0x40u) divider: 0 - /1 */

#define ID_1 (1*0x40u) divider: 1 - /2 */

#define ID_2 (2*0x40u) divider: 2 - /4 */

#define ID_3 (3*0x40u) divider: 3 - /8 */

#define TASSEL_0 (0*0x100u) source select: 0 - TACLK */

#define TASSEL_1 (1*0x100u) source select: 1 - ACLK */

#define TASSEL_2 (2*0x100u) source select: 2 - SMCLK */

#define TASSEL_3 (3*0x100u) source select: 3 - INCLK */

#define CM1 (0x8000) #define CM0 (0x4000) /* Timer A counter /* Timer A counter /* Timer A counter /* Timer A mode /* Timer A mode /* Timer A mode /* Timer A mode /* Timer A input /* Timer A input /* Timer A input /* Timer A input /* Timer A clock /* Timer A clock /* Timer A clock /* Timer A clock /* Capture mode 1 */ /* Capture mode 0 */

#define CCIS1 (0x2000) /* Capture input select 1 */

#define CCIS0 (0x1000) /* Capture input select 0 */ #define SCS (0x0800) /* Capture sychronize */

#define SCCI (0x0400) /* Latched capture signal (read) */

#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */

#define OUTMOD2 (0x0080) #define OUTMOD1 (0x0040) #define OUTMOD0 (0x0020) #define CCIE (0x0010) interrupt enable */

#define CCI (0x0008) signal (read) */

#define OUT (0x0004) if output mode 0 */

#define COV (0x0002) overflow flag */

#define CCIFG (0x0001) interrupt flag */

#define OUTMOD_0 (0*0x20u) 0 - output only */

#define OUTMOD_1 (1*0x20u) 1 - set */

#define OUTMOD_2 (2*0x20u) 2 - PWM toggle/reset */#define OUTMOD_3 (3*0x20u) 3 - PWM set/reset */

#define OUTMOD_4 (4*0x20u) 4 - toggle */

#define OUTMOD_5 (5*0x20u) 5 - Reset */

#define OUTMOD_6 (6*0x20u) 6 - PWM toggle/set */

#define OUTMOD_7 (7*0x20u) 7 - PWM reset/set */

#define CCIS_0 (0*0x1000u) select: 0 - CCIxA */

#define CCIS_1 (1*0x1000u) select: 1 - CCIxB */

/* Output mode 2 */ /* Output mode 1 */ /* Output mode 0 */ /* Capture/compare /* Capture input /* PWM Output signal /* Capture/compare /* Capture/compare /* PWM output mode: /* PWM output mode: /* PWM output mode: /* PWM output mode: /* PWM output mode: /* PWM output mode: /* PWM output mode: /* PWM output mode: /* Capture input /* Capture input

#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */

#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */

#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */

#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */

#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */

#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */

/* T0_A3IV Definitions */

#define TA0IV_NONE (0x0000) /* No Interrupt pending */

#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */ #define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */ #define TA0IV_6 (0x0006) /* Reserved */ #define TA0IV_8 (0x0008) /* Reserved */ #define TA0IV_TAIFG (0x000A) /* TA0IFG */

/************************************************************ * Timer1_A3

************************************************************/ #define __MSP430_HAS_T1A3__ /* Definition to show that Module is available */

SFR_16BIT(TA1IV); /* Timer1_A3 Interrupt Vector Word */

SFR_16BIT(TA1CTL); /* Timer1_A3 Control */

SFR_16BIT(TA1CCTL0); /* Timer1_A3 Capture/Compare Control 0 */

SFR_16BIT(TA1CCTL1); /* Timer1_A3 Capture/Compare Control 1 */

SFR_16BIT(TA1CCTL2); /* Timer1_A3 Capture/Compare Control 2 */

SFR_16BIT(TA1R); /* Timer1_A3 */ SFR_16BIT(TA1CCR0); /* Timer1_A3 Capture/Compare 0 */

SFR_16BIT(TA1CCR1); /* Timer1_A3 Capture/Compare 1 */

SFR_16BIT(TA1CCR2); /* Timer1_A3

Capture/Compare 2 */

/* Bits are already defined within the Timer0_Ax */

/* T1_A3IV Definitions */

#define TA1IV_NONE (0x0000) /* No Interrupt pending */

#define TA1IV_TACCR1 (0x0002) /* TA1CCR1_CCIFG */ #define TA1IV_TACCR2 (0x0004) /* TA1CCR2_CCIFG */ #define TA1IV_TAIFG (0x000A) /* TA1IFG */

/************************************************************ * USCI

************************************************************/ #define __MSP430_HAS_USCI__ /* Definition to show that Module is available */

SFR_8BIT(UCA0CTL0); /* USCI A0 Control Register 0 */

SFR_8BIT(UCA0CTL1); /* USCI A0 Control Register 1 */

SFR_8BIT(UCA0BR0); /* USCI A0 Baud Rate 0 */

SFR_8BIT(UCA0BR1); /* USCI A0 Baud Rate 1 */

SFR_8BIT(UCA0MCTL); /* USCI A0 Modulation Control */

SFR_8BIT(UCA0STAT); /* USCI A0 Status Register */

SFR_8BIT(UCA0RXBUF); /* USCI A0 Receive Buffer */

SFR_8BIT(UCA0TXBUF); /* USCI A0 Transmit Buffer */

SFR_8BIT(UCA0ABCTL); /* USCI A0 LIN Control */

SFR_8BIT(UCA0IRTCTL); /* USCI A0 IrDA Transmit Control */

SFR_8BIT(UCA0IRRCTL); /* USCI A0 IrDA Receive Control */

SFR_8BIT(UCB0CTL0); /* USCI B0 Control Register 0 */

SFR_8BIT(UCB0CTL1); /* USCI B0 Control Register 1 */

SFR_8BIT(UCB0BR0); /* USCI B0 Baud Rate 0 */

SFR_8BIT(UCB0BR1); /* USCI B0 Baud Rate 1 */

SFR_8BIT(UCB0I2CIE); /* USCI B0 I2C Interrupt Enable Register */

SFR_8BIT(UCB0STAT); /* USCI B0 Status Register */

SFR_8BIT(UCB0RXBUF); Buffer */

SFR_8BIT(UCB0TXBUF); Buffer */

SFR_16BIT(UCB0I2COA); Address */

SFR_16BIT(UCB0I2CSA); Address */

// UART-Mode Bits

#define UCPEN (0x80) Parity enable */

#define UCPAR (0x40) Parity 0:odd / 1:even */

#define UCMSB (0x20) first 0:LSB / 1:MSB */

#define UC7BIT (0x10) Bits 0:8-bits / 1:7-bits */#define UCSPB (0x08) Bits 0:one / 1: two */

#define UCMODE1 (0x04) Mode 1 */

#define UCMODE0 (0x02) Mode 0 */

#define UCSYNC (0x01) 0:UART-Mode / 1:SPI-Mode */

// SPI-Mode Bits

#define UCCKPH (0x80) Phase */

#define UCCKPL (0x40) Polarity */ #define UCMST (0x08) Select */

/* USCI B0 Receive /* USCI B0 Transmit /* USCI B0 I2C Own /* USCI B0 I2C Slave /* Async. Mode: /* Async. Mode: /* Async. Mode: MSB /* Async. Mode: Data /* Async. Mode: Stop /* Async. Mode: USCI /* Async. Mode: USCI /* Sync-Mode /* Sync. Mode: Clock /* Sync. Mode: Clock /* Sync. Mode: Master

// I2C-Mode Bits

#define UCA10 (0x80) /* 10-bit Address Mode */

#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */

#define UCMM (0x20) /* Multi-Master Environment */

//#define res (0x10) /* reserved */

#define UCMODE_0 (0x00) Mode: 0 */

#define UCMODE_1 (0x02) Mode: 1 */

#define UCMODE_2 (0x04) Mode: 2 */

#define UCMODE_3 (0x06) Mode: 3 */

// UART-Mode Bits

#define UCSSEL1 (0x80) Source Select 1 */#define UCSSEL0 (0x40) Source Select 0 */#define UCRXEIE (0x20) enable */

#define UCBRKIE (0x10) enable */

#define UCDORM (0x08) Mode */

#define UCTXADDR (0x04) Address */

#define UCTXBRK (0x02) Break */

#define UCSWRST (0x01) Reset */

// SPI-Mode Bits

//#define res (0x20) /* reserved *///#define res (0x10) /* reserved *///#define res (0x08) /* reserved *///#define res (0x04) /* reserved *///#define res (0x02) /* reserved */

// I2C-Mode Bits

/* Sync. Mode: USCI /* Sync. Mode: USCI /* Sync. Mode: USCI /* Sync. Mode: USCI /* USCI 0 Clock /* USCI 0 Clock /* RX Error interrupt /* Break interrupt /* Dormant (Sleep) /* Send next Data as /* Send next Data as /* USCI Software

//#define res (0x20) /* reserved */

#define UCTR (0x10) /* Transmit/Receive Select/Flag */

#define UCTXNACK (0x08) /* Transmit NACK */ #define UCTXSTP (0x04) /* Transmit STOP */ #define UCTXSTT (0x02) /* Transmit START */ #define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */

#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */

#define UCSSEL_2 (0x80) Source: 2 */

#define UCSSEL_3 (0xC0) Source: 3 */

#define UCBRF3 (0x80) Modulation Select 3 */#define UCBRF2 (0x40) Modulation Select 2 */#define UCBRF1 (0x20) Modulation Select 1 */#define UCBRF0 (0x10) Modulation Select 0 */#define UCBRS2 (0x08) Modulation Select 2 */#define UCBRS1 (0x04) Modulation Select 1 */#define UCBRS0 (0x02) Modulation Select 0 */#define UCOS16 (0x01) Oversampling enable */

#define UCBRF_0 (0x00) Modulation: 0 */

#define UCBRF_1 (0x10) Modulation: 1 */

#define UCBRF_2 (0x20) Modulation: 2 */

#define UCBRF_3 (0x30) Modulation: 3 */

#define UCBRF_4 (0x40) Modulation: 4 */

#define UCBRF_5 (0x50) Modulation: 5 */

/* USCI 0 Clock /* USCI 0 Clock /* USCI First Stage /* USCI First Stage /* USCI First Stage /* USCI First Stage /* USCI Second Stage /* USCI Second Stage /* USCI Second Stage /* USCI 16-times /* USCI First Stage /* USCI First Stage /* USCI First Stage /* USCI First Stage /* USCI First Stage /* USCI First Stage

#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */

#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */

#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */

#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */

#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */

#define UCBRF_11 (0xB0) Modulation: B */

#define UCBRF_12 (0xC0) Modulation: C */

#define UCBRF_13 (0xD0) Modulation: D */

#define UCBRF_14 (0xE0) Modulation: E */

#define UCBRF_15 (0xF0) Modulation: F */

#define UCBRS_0 (0x00) Modulation: 0 */

#define UCBRS_1 (0x02) Modulation: 1 */

#define UCBRS_2 (0x04) Modulation: 2 */

#define UCBRS_3 (0x06) Modulation: 3 */

#define UCBRS_4 (0x08) Modulation: 4 */

#define UCBRS_5 (0x0A) Modulation: 5 */

#define UCBRS_6 (0x0C) Modulation: 6 */

#define UCBRS_7 (0x0E) Modulation: 7 */

#define UCLISTEN (0x80) */

#define UCFE (0x40) Flag */ #define UCOE (0x20) Flag */

/* USCI First Stage /* USCI First Stage /* USCI First Stage /* USCI First Stage /* USCI First Stage /* USCI Second Stage /* USCI Second Stage /* USCI Second Stage /* USCI Second Stage /* USCI Second Stage /* USCI Second Stage /* USCI Second Stage /* USCI Second Stage /* USCI Listen mode /* USCI Frame Error /* USCI Overrun Error

#define UCPE (0x10) /* USCI Parity Error Flag */

#define UCBRK (0x08) /* USCI Break received */

#define UCRXERR (0x04) /* USCI RX Error Flag */

#define UCADDR (0x02) /* USCI Address received Flag */

#define UCBUSY (0x01) /* USCI Busy Flag */ #define UCIDLE (0x02) detected Flag */

//#define res (0x80) /* reserved *///#define res (0x40) /* reserved *///#define res (0x20) /* reserved *///#define res (0x10) /* reserved */#define UCNACKIE (0x08) interrupt enable */

#define UCSTPIE (0x04) interrupt enable */

#define UCSTTIE (0x02) interrupt enable */

#define UCALIE (0x01) interrupt enable */

#define UCSCLLOW (0x40) #define UCGC (0x20) address received Flag */#define UCBBUSY (0x10) #define UCNACKIFG (0x08) interrupt Flag */

#define UCSTPIFG (0x04) interrupt Flag */

#define UCSTTIFG (0x02) interrupt Flag */

#define UCALIFG (0x01) interrupt Flag */

#define UCIRTXPL5 (0x80) Pulse Length 5 */

#define UCIRTXPL4 (0x40) Pulse Length 4 */

#define UCIRTXPL3 (0x20) Pulse Length 3 */

/* USCI Idle line

/* NACK Condition /* STOP Condition /* START Condition /* Arbitration Lost /* SCL low */ /* General Call /* Bus Busy Flag */ /* NAK Condition /* STOP Condition /* START Condition /* Arbitration Lost /* IRDA Transmit /* IRDA Transmit /* IRDA Transmit

#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */

#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */

#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */

#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */

#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */

#define UCIRRXFL5 (0x80) Filter Length 5 */

#define UCIRRXFL4 (0x40) Filter Length 4 */

#define UCIRRXFL3 (0x20) Filter Length 3 */

#define UCIRRXFL2 (0x10) Filter Length 2 */

#define UCIRRXFL1 (0x08) Filter Length 1 */

#define UCIRRXFL0 (0x04) Filter Length 0 */ #define UCIRRXPL (0x02) Polarity */

#define UCIRRXFE (0x01) Filter enable */

//#define res (0x80) /* reserved *///#define res (0x40) /* reserved */#define UCDELIM1 (0x20) Delimiter 1 */

#define UCDELIM0 (0x10) Delimiter 0 */

#define UCSTOE (0x08) Timeout error */

#define UCBTOE (0x04) error */

//#define res (0x02) /* reserved */#define UCABDEN (0x01) detect enable */

#define UCGCEN (0x8000) enable */

/* IRDA Receive /* IRDA Receive /* IRDA Receive /* IRDA Receive /* IRDA Receive /* IRDA Receive /* IRDA Receive Input /* IRDA Receive

/* Break Sync /* Break Sync /* Sync-Field /* Break Timeout

/* Auto Baud Rate /* I2C General Call #define UCOA9 (0x0200) /* I2C Own Address 9 */

#define UCOA8 (0x0100) /* I2C Own Address 8 */

#define UCOA7 (0x0080) /* I2C Own Address 7 */

#define UCOA6 (0x0040) /* I2C Own Address 6 */

#define UCOA5 (0x0020) /* I2C Own Address 5 */

#define UCOA4 (0x0010) /* I2C Own Address 4 */

#define UCOA3 (0x0008) /* I2C Own Address 3 */

#define UCOA2 (0x0004) /* I2C Own Address 2 */

#define UCOA1 (0x0002) /* I2C Own Address 1 */

#define UCOA0 (0x0001) /* I2C Own Address 0 */

#define UCSA9 (0x0200) /* I2C Slave Address 9 */

#define UCSA8 (0x0100) /* I2C Slave Address 8 */

#define UCSA7 (0x0080) /* I2C Slave Address 7 */

#define UCSA6 (0x0040) /* I2C Slave Address 6 */

#define UCSA5 (0x0020) /* I2C Slave Address 5 */

#define UCSA4 (0x0010) /* I2C Slave Address 4 */

#define UCSA3 (0x0008) /* I2C Slave Address 3 */

#define UCSA2 (0x0004) /* I2C Slave Address 2 */

#define UCSA1 (0x0002) /* I2C Slave Address 1 */

#define UCSA0 (0x0001) /* I2C Slave Address 0 */

/************************************************************ * WATCHDOG TIMER

************************************************************/ #define __MSP430_HAS_WDT__ /* Definition to show that Module is available */

SFR_16BIT(WDTCTL); /* Watchdog Timer Control */

/* The bit names have been prefixed with \ #define WDTIS0 (0x0001) #define WDTIS1 (0x0002) #define WDTSSEL (0x0004) #define WDTCNTCL (0x0008) #define WDTTMSEL (0x0010) #define WDTNMI (0x0020) #define WDTNMIES (0x0040) #define WDTHOLD (0x0080)

#define WDTPW (0x5A00)

/* WDT-interval times [1ms] coded with Bits 0-2 */ /* WDT is clocked by fSMCLK (assumed 1MHz) */

#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */

#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms \

#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms \

#define WDT_MDLY_0_064

(WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms \*/ /* WDT is clocked by fACLK (assumed 32KHz) */

#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms \

#define WDT_ADLY_250

(WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms \*/ #define WDT_ADLY_16

(WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms \*/ #define WDT_ADLY_1_9

(WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms \*/

/* Watchdog mode -> reset after expired time */ /* WDT is clocked by fSMCLK (assumed 1MHz) */

#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */

#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms \

#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms \

#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms \

/* WDT is clocked by fACLK (assumed 32KHz) */

#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms \

#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms \

#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms \

#define WDT_ARST_1_9

(WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms \*/

/* INTERRUPT CONTROL */

/* These two bits are defined in the Special Function Registers */

/* #define WDTIE 0x01 */ /* #define WDTIFG 0x01 */

/************************************************************ * Calibration Data in Info Mem

************************************************************/

#ifndef __DisableCalData

SFR_8BIT(CALDCO_16MHZ); /* DCOCTL Calibration Data for 16MHz */

SFR_8BIT(CALBC1_16MHZ); /* BCSCTL1 Calibration Data for 16MHz */

SFR_8BIT(CALDCO_12MHZ); /* DCOCTL Calibration Data for 12MHz */

SFR_8BIT(CALBC1_12MHZ); /* BCSCTL1 Calibration Data for 12MHz */

SFR_8BIT(CALDCO_8MHZ); /* DCOCTL Calibration Data for 8MHz */

SFR_8BIT(CALBC1_8MHZ); /* BCSCTL1 Calibration Data for 8MHz */

SFR_8BIT(CALDCO_1MHZ); /* DCOCTL Calibration Data for 1MHz */

SFR_8BIT(CALBC1_1MHZ); /* BCSCTL1 Calibration Data for 1MHz */

#endif /* #ifndef __DisableCalData */

/************************************************************ * Interrupt Vectors (offset from 0xFFE0)

************************************************************/

#define VECTOR_NAME(name) name##_ptr #define EMIT_PRAGMA(x) _Pragma(#x) #define CREATE_VECTOR(name) void (* const VECTOR_NAME(name))(void) = &name

#define PLACE_VECTOR(vector,section)

EMIT_PRAGMA(DATA_SECTION(vector,section))

#define ISR_VECTOR(func,offset) CREATE_VECTOR(func); \\

PLACE_VECTOR(VECTOR_NAME(func), offset)

#ifdef __ASM_HEADER__ /* Begin #defines for assembler */ #define PORT1_VECTOR \ /* 0xFFE4 Port 1 */ #else

#define PORT1_VECTOR (2 * 1u) /* 0xFFE4 Port 1 */

/*#define PORT1_ISR(func) ISR_VECTOR(func, \ /* 0xFFE4 Port 1 */ /* CCE V2 Style */ #endif

#ifdef __ASM_HEADER__ /* Begin #defines for assembler */ #define PORT2_VECTOR \ /* 0xFFE6 Port 2 */ #else

#define PORT2_VECTOR (3 * 1u) /* 0xFFE6 Port 2 */

/*#define PORT2_ISR(func) ISR_VECTOR(func, \ /* 0xFFE6 Port 2 */ /* CCE V2 Style */ #endif

#ifdef __ASM_HEADER__ /* Begin #defines for assembler */ #define ADC10_VECTOR \ /* 0xFFEA ADC10 */ #else

#define ADC10_VECTOR (5 * 1u) /* 0xFFEA ADC10 */

/*#define ADC10_ISR(func) ISR_VECTOR(func, \ /* 0xFFEA ADC10 */ /* CCE V2 Style */ #endif

#ifdef __ASM_HEADER__ /* Begin #defines for assembler */ #define USCIAB0TX_VECTOR \ /*

0xFFEC USCI A0/B0 Transmit */ #else

#define USCIAB0TX_VECTOR (6 * 1u) /* 0xFFEC USCI A0/B0 Transmit */

/*#define USCIAB0TX_ISR(func) ISR_VECTOR(func, \ /* 0xFFEC USCI A0/B0 Transmit */ /* CCE V2 Style */ #endif

#ifdef __ASM_HEADER__ /* Begin #defines for assembler */ #define USCIAB0RX_VECTOR \ /* 0xFFEE USCI A0/B0 Receive */ #else

#define USCIAB0RX_VECTOR (7 * 1u) /* 0xFFEE USCI A0/B0 Receive */

/*#define USCIAB0RX_ISR(func) ISR_VECTOR(func, \ /* 0xFFEE USCI A0/B0 Receive */ /* CCE V2 Style */ #endif

#ifdef __ASM_HEADER__ /* Begin #defines for assembler */ #define TIMER0_A1_VECTOR \ /* 0xFFF0 Timer0)A CC1, TA0 */ #else

#define TIMER0_A1_VECTOR (8 * 1u) /* 0xFFF0 Timer0)A CC1, TA0 */

/*#define TIMER0_A1_ISR(func) ISR_VECTOR(func, \ /* 0xFFF0 Timer0)A CC1, TA0 */ /* CCE V2 Style */ #endif

#ifdef __ASM_HEADER__ /* Begin #defines for assembler */ #define TIMER0_A0_VECTOR \ /* 0xFFF2 Timer0_A CC0 */ #else

#define TIMER0_A0_VECTOR (9 * 1u) /* 0xFFF2 Timer0_A CC0 */

/*#define TIMER0_A0_ISR(func) ISR_VECTOR(func, \ /* 0xFFF2 Timer0_A CC0 */ /* CCE V2 Style */ #endif

#ifdef __ASM_HEADER__ /* Begin #defines for assembler */ #define WDT_VECTOR \ /* 0xFFF4 Watchdog Timer */ #else

#define WDT_VECTOR (10 * 1u) /* 0xFFF4 Watchdog Timer */

/*#define WDT_ISR(func) ISR_VECTOR(func, \ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */ #endif

#ifdef __ASM_HEADER__ /* Begin #defines for assembler */

#define COMPARATORA_VECTOR \ /* 0xFFF6 Comparator A */ #else

#define COMPARATORA_VECTOR (11 * 1u) /* 0xFFF6 Comparator A */

/*#define COMPARATORA_ISR(func) ISR_VECTOR(func, \ /* 0xFFF6 Comparator A */ /* CCE V2 Style */ #endif

#ifdef __ASM_HEADER__ /* Begin #defines for assembler */ #define TIMER1_A1_VECTOR \ /* 0xFFF8 Timer1_A CC1-4, TA1 */ #else

#define TIMER1_A1_VECTOR (12 * 1u) /* 0xFFF8 Timer1_A CC1-4, TA1 */

/*#define TIMER1_A1_ISR(func) ISR_VECTOR(func, \ /* 0xFFF8 Timer1_A CC1-4, TA1 */ /* CCE V2 Style */ #endif

#ifdef __ASM_HEADER__ /* Begin #defines for assembler */ #define TIMER1_A0_VECTOR \ /* 0xFFFA Timer1_A CC0 */ #else

#define TIMER1_A0_VECTOR (13 * 1u) /* 0xFFFA Timer1_A CC0 */

/*#define TIMER1_A0_ISR(func) ISR_VECTOR(func, \ /* 0xFFFA Timer1_A CC0 */ /* CCE V2 Style */ #endif

#ifdef __ASM_HEADER__ /* Begin #defines for assembler */ #define NMI_VECTOR \ /* 0xFFFC Non-maskable */ #else

#define NMI_VECTOR (14 * 1u) /* 0xFFFC Non-maskable */

/*#define NMI_ISR(func) ISR_VECTOR(func, \ /* 0xFFFC Non-maskable */ /* CCE V2 Style */ #endif

#ifdef __ASM_HEADER__ /* Begin #defines for assembler */ #define RESET_VECTOR \ /* 0xFFFE Reset [Highest Priority] */ #else

#define RESET_VECTOR (15 * 1u) /* 0xFFFE Reset [Highest Priority] */

/*#define RESET_ISR(func) ISR_VECTOR(func, \ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */ #endif

/************************************************************ * End of Modules

************************************************************/

#ifdef __cplusplus }

#endif /* extern \

#endif /* #ifndef __MSP430G2553 */

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