boundary scan技术资料

边界扫描(Boundary scan )是一项测试技术，是在传统的在线测试不在适应大规模，高集成电路测试的情况下而提出的，就是在IC设计的过程中在IC的内部逻辑和每个器件引脚间放置移位寄存器(shift register).每个移位寄存器叫做一个CELL。这些CELL准许你去控制和观察每个输入/输出引脚的状态。当这些CELL连在一起就形成了一个数据寄存器链(data register chain),我门叫它边界寄存器(boundaryregister)。除了上面的移位寄存器外，在IC上还集成测试访问端口控制器 (TAP controller),指令寄存器(Instruction register)对边界扫描的指令进行解码以便执行各种测试功能。旁路寄存器(bypass register)提供一个最短的测试通路。另外可能还会有IDCODE register和其它符合标准的用户特殊寄存器。

下图是一个典型的具有边界扫描功能的IC。

此主题相关图片如下：

边界扫描器件典型特征及边界扫描测试信号的构成。

如果一个器件是边界扫描器件它一定有下面5个信号中的前四个：

1．TDI (测试数据输入)

2．TDO (侧试数据输出)

3．TMS (测试模式选择输入)

4．TCK (测试时钟输入)

5．TRST (测试复位输入，这个信号是可选的)

TMS,TCK,TRST构成了边界扫描测试端口控制器(TAP controller)，它负责测试信号指令的输入，输出，指令解码等，TAP controller是一个16位的状态机，

边界扫描测试的每个环节都由它来控制，所以要对TAP controller有一个比较清楚的了解。

在后续的文章中还会向大家介绍边界扫描的其它方面。

边界扫描为开发人员缩短开发周期，并且提供良好的覆盖率和诊断信息。在不了解

IC内部逻辑的情况下快速的开发出优秀的测试程序。在未来的测试领域，边界扫描将会得到广泛的应用。

摘要：通过JTAG实现对Flash在线编程。首先，介绍JTAG的定义、结构及引脚的定义，并阐述JTAG状态机的工作原理。然后，介绍JTAG口的边界扫描寄存器，给出实现JTAG在

线写Flash的电路，和如何通过JTAG实现Flash的编程及程序流程图。

关键词：JTAG Flash 在线编程

随着嵌入式技术的发展，在一些高端的掌上设备中，都使用了Flash芯片，如Compaq的iPAQ、联想的天祺系列等产品。但对于研发人员来说，在开发阶段需要大量的程序调试，就意味着要对Flash进行擦除和改写的工作，因此，如何对Flash进行在线编程是问题的关

键所在。本文介绍一种通过JTAG对Flash进行的在线编程方法。

1 JTAG简介

JTAG（Joint Test Action Group）是1985年制定的检测PCB和IC芯片的一个标准，1990年被修改后成为IEEE的一个标准，即IEEE1149.1-1990。通过这个标准，可对

具有JTAG口芯片的硬件电路进行边界扫描和故障检测。

图1 TAP控制器的状态机框图

具有JTAG口的芯片都有如下JTAG引脚定义：

TCK——测试时钟输入；

TDI——测试数据输入，数据通过TDI输入JTAG口； TDO——测试数据输出，数据通过TDO从JTAG口输出；

TMS——测试模式选择，TMS用来设置JTAG口处于某种特定的测试模式。

可选引脚TRST——测试复位，输入引脚，低电平有效。 含有JTAG口的芯片种类较多，如CPU、DSP、CPLD等。

JTAG内部有一个状态机，称为TAP控制器。TAP控制器的状态机通过TCK和TMS进行状态的改变，实现数据和指令的输入。图1为TAP控制器的状态机框图。

2 JTAG芯片的边界扫描寄存器

JTAG标准定义了一个串行的移位寄存器。寄存器的每一个单元分配给IC芯片的相应引脚，每一个独立的单元称为BSC（Boundary-Scan Cell）边界扫描单元。这个串联的BSC在IC内部构成JTAG回路，所有的BSR（Boundary-Scan Register）边界扫描寄存器通过JTAG测试激活，平时这些引脚保持正常的IC功能。图2为具有JTAG口的IC内部BSR单

元与引脚的关系。

3 JTAG在线写Flash的硬件电路设计和与PC的连接方式

以含JTAG接口的StrongARM SA1110为例，Flash为Intel 28F128J32 16MB容量。SA1110的JTAG的TCK、TDI、TMS、TDO分别接PC并口的2、3、4、11线上，通过程序将对JTAG口的控制指令和目标代码从PC的并口写入JTAG的BSR中。在设计PCB时，必须将SA1110的数据线和地址线及控制线与Flash的地线线、数据线和控制线相连。因SA1110的数据线、地址线及控制线的引脚上都有其相应BSC，只要用JTAG指令将

数据、地址及控制信号送到其BSC中，就可通过BSC对应的引脚将信号送给Flash，实现对

Flash的操作。JTAG的系统板设计和连线关系如图3所示。

4 通过使用TAP状态机的指令实行对Flash的操作

通过TCK、TMS的设置，可将JTAG设置为接收指令或数据状态。JTAG常用指令如

下：

SAMPLE/PRELOAD——用此指令采样BSC内容或将数据写入BSC单元； EXTEST——当执行此指令时，BSC的内容通过引脚送到其连接的相应芯片的引脚，我

们就是通过这种指令实现在线写Flash的；

BYPASS——此指令将一个一位寄存器轩于BSC的移位回路中，即仅有一个一位寄存器

处于TDI和TDO之间。

在PCB电路设计好后，即可用程序先将对JTAG的控制指令，通过TDI送入JTAG控制器的指令寄存器中。再通过TDI将要写Flash的地址、数据及控制线信号入BSR中，并将数

据锁存到BSC中，用EXTEST指令通过BSC将写入Flash。

5 软件编程

在线写Flash的程序用Turbo C编写。程序使用PC的并行口，将程序通过含有JTAG的芯片写入Flash芯片。程序先对PC的并口初始化，对JTAG口复位和测试，并读Flash，判断是否加锁。如加锁，必须先解锁，方可进行操作。写Flash之前，必须对其先擦除。将J

TAG芯片设置在EXTEST模式，通过PC的并口，将目标文件通过JTAG写入Flash，并在

烧写完成后进行校验。程序主流程如图4所示。

通过JTAG的读芯片ID子程序如下：

void id_command(void){

putp(1,0,IP); //Run-Test/Idle;使JTAG复位

putp(1,0,IP); //Run-Test/Idle putp(1,0,IP); //Run-Test/Idle putp(1,0,IP); //Run-Test/Idle

putp(1,1,IP);

putp(1,1,IP); //选择指令寄存器 putp(1,0,IP); //捕获指令寄存器 putp(1,0,IP); /移位指令寄存器

putp(0,0,IP); //SA1110JTAG口指令长度5位，IDCODE为01100

putp(1,0,IP); putp(1,0,IP); putp(0,0,IP); putp(0,0,IP);

putp(0,1,IP); //退出指令寄存器

putp(1,1,IP); //更新指令寄存器，执行指令寄存器中的指令

putp(1,0,IP)； //Run-Test/Idle putp(1,0,IP); //Run-Test/Idle putp(1,0,IP); //Run-Test/Idle

putp(1,1,IP); putp(1,0,IP); if(check_id(SA1110ID))

error_out(\

0\

putp(1,1,IP); //退出数据寄存器 putp(1,1,IP); //更新数据寄存器

putp(1,0,IP); //Run-Test/Idle,使JTAG复位

putp(1,0,IP); //Run-Test/Idle putp(1,0,IP); //Run-Test/Idle

}

6 电路设计和编程中的注意事项

①Flash芯片的WE、CE、OE等控制线必须与SA1110的BSR相连。只有这样，才能

通过BSR控制Flash的相应引脚。

②JTAG口与PC并口的连接线要尽量短，原则上不大于15cm。

③Flash在擦写和编程时所需的工作电流较大，在选用系统的供电芯片时，必须加以考

虑。

④为提高对Flash的编程速度，尽量使TCK不低于6MHz，可编写烧写Flash程序时实

现。

JTAG口及其对Flash的在线编程-单片机技术JTAG口及其对Flash的在线编程

A Brief Introduction to the JTAG

Boundary Scan Interface

Nick Patavalis (npat@inaccessnetworks.com)

Athens 08 Nov 2001

One of the difficult areas in the development of any modern hardware system is the production-testing of the Printed Circuit Boards (PCBs). This is the problem addressed by the IEEE standard number 1149 \

Architecture\the signal-levels on the pins of a digital circuit, and has some extensions for testing the internal circuitry on the chip itself (which will not be discussed here). The standard was written by the Joint Test Action Group (JTAG) and the architecture defined by it is known as \

The general structure of the JTAG boundary scan test interface is shown in the following figure.

All the signals between the chip's core logic and the pins are intercepted by a serial scan path known as the \Boundary Scan Register\BSR), and shown as cells \\

transparently connect the core-logic signals to the pins and effectively become invisible. In external-test mode, it can disconnect the core-logic from the pins, drive the output pins (\input pins (figure: \logic from the pins, drive the core-logic input signals by itself, and read and latch the states of the core-logic output signals.

In the figure above, and assuming that the JTAG interface is in external-test mode, C0 is the BSR cell capturing the state of the input pin 0. C1 is the BSR cell driving the output pin 1. C2 does not itself correspond to any specific pin, but it is the \which controls the \

capturing the state of the bidirectional pin 2, and C4 is the output BSR cell driving the bidirectional pin 2. Summarizing we can identify three times of BSR cells:

?

Input Cells like C0, and C3. They are always associated with a specific pin whose state they capture when the JTAG interface is in external test mode.

Output Cells like C1, and C4. They are always associated with a specific pin which they drive when the JTAG interface is in external test mode.

? Enable Cells like C2. They are not associated with any pin per-se, but they either control the direction of bidirectional pins, or enable and disable certain input or output pins.

?

Gates E0, E3, and E4 operate under the control of the TAP (and probably also under the control of \respective input, or output, cells to, or from, the chip's pins. The state capture, or

application, takes place during certain transitions of the TAP state-machine, and only if the IR (instruction register) has been previously loaded with, and contains, the proper opcode (e.g. EXTEST).

Gates I0, I3, and I4 operate under the control of the TAP (and probably also under the control of \respective input, or output, cells to, or from, the chip's internal-logic signal lines. The capture, or application, takes place during certain transitions of the TAP state-machine, and only if the IR (instruction register) has been previously loaded with, and contains, the proper opcode (e.g. INTEST).

Gates N0, N1, and N3, come into operation only when the system is in normal-operation mode (i.e. when the JTAG test apparatus is inactive) and connect the chip's pins to the internal core-logic signals, as if the Boundary Scan Path was not present.

The contents of the BSR register can be written and read bit-after-bit, in a serial fashion, using the TDI and TDO JTAG signals. Actually the BSR \

operations take place at the same time, with the new \the previous value is shifted out from TDO. The same technique is used to read and write the values of the other JTAG registers too, by having the TAP controller connect them between the TDI and TDO pins, in place of the BSR.

Interface signals

The JTAG interface uses the following five dedicated signals which must be provided on each chip that supports the standard:

TRST* is a Test-ReSeT input which initializes and disables the test interface. TCK is the Test CLocK input which controls the timing of the test interface independently from any system clocks. TCK is pulsed by the equipment

controlling the test and not by the tested device. It can be pulsed at any frequency (up to a maximum of some MHz). It can be even pulsed at varying rates. ? TMS is the Test Mode Select input which controls the transitions of the test interface state machine.

? TDI is the Test Data Input line, which supplies the data to the JTAG registers (Boundary Scan Register, Instruction Register, or other data registers).

? ?

?

TDO is the Test Data Output line, which is used to serially output the data from the JTAG registers to the equipment controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit.

The normal organization of the test circuit on a board that incorporates several chips with JTAG support is to connect TRST*, TCK, and TMS to every chip in parallel, and to connect TDO from one chip to TDI of the next in a single loop. This way the board presents a single test interface that has the same five signals discussed above. A simpler arrangement, for boards that have only a few chips with JTAG interfaces, is to provide one JTAG test-port for every such chip, and control the tests independently.

The TAP controller

The operation of the test interface is controlled by the Test Access Port (TAP) controller. This is a state-machine whose state transitions are controller by the TMS signal; the state-transition diagram is shown in the following figure.

As you can see all the states have two exits, so all the transitions can be controlled by one signal, TMS. The two main paths in the state transition diagram control the operations on the Data Registers (ID register, Bypass register, BSR register), and the Instruction Register. The Data Register operated upon every time the DR path is taken is selected based on the value loaded in the Instruction Register.

A transition path like the following (informally called \ir path\value into the Instruction Register, and read the old value back:

*-> test logic reset --> run test idle --> select dr scan --> select ir scan --> capture ir

--> shift ir --> ... n times ... --> shift ir --> exit1 ir --> update ir

--> run test idle ->*

The new value is shifted-in the Instruction Register from the TDI line---one bit at a time---upon the entries to the 'shift ir' state. The old value of the Instruction Register is shifted-out the TDO line---one bit at a time---upon the exits from the \A transition path like the following (informally called \dr path\value into the currently selected Data Register, and read the old value back:

*-> test logic reset --> run test idle --> select dr scan --> capture dr

--> shift dr --> ... n times ... --> shift dr --> exit1 dr --> update dr

--> run test idle ->*

The new value is shifted-in the currently selected Data Register from the TDI line---one bit at a time---upon the entries to the 'shift dr' state. The old value of the current selected Data Register is shifted-out to the TDO line---one bit at a time---upon the exits from the \

\Data Register, that will be shifted out, is \state. The new value shifted-in the Instruction Register, is applied (and the instruction takes effect) upon the entry to the \Data Register is applied (e.g transfered to the output pins, in case of the BSR) upon the entry to the \

Data Registers

As has been mentioned, the behavior of the test operation is affected by the contents of the instruction register, which selects between various different data registers to be

operated upon during a \JTAG implementation:

?

The Device ID register (IDR) reads-out an identification number which is hardwired into the chip.

The Bypass register (BR) is a 1-cell pass-through register which connects the TDI to the TDO with a 1-clock delay to give test equipment easy access to another device in the test chain on the same board.

? The Boundary Scan register (BSR), which has been described in detail above, intercepts all the signals between the core-logic and the pins.

?

Other registers may also be present on the chip, to perform other test operations

Instructions

The normal way of performing a JTAG test operation is to enter an instruction which specifies the type of test to be performed next, and the Data Register to be used during this test, into the Instruction Register (by means of running the TAP through an \and then to use the Data Register to perform the test (by means of running the TAP through one or more \

There are private and public instructions. Public instructions are documented by the chip manufacturers and available for general use. Private instructions are not. The IEEE-1149 standard defines a mandatory set of public instructions that must be present in all

compliant JTAG implementations. This mandatory set contains the following instructions: BYPASS: Here the TDI and TDO lines are connected to single-bit pass-through register (which passes to TDI to the TDO with a single-clock delay). This

instruction allows the testing of other devices connected to the same test-loop. ? EXTEST: With this command the boundary scan register (BSR) is connected between the TDI and the TDO signals. The chip's pin states are sampled and captured by the BSR cells at the entry to the \transition diagram above). The contents of the BSR register are shifted out via the TDO line at exits from the \

captured data) are shifted out, new data are sifted in at the entries to the \state. The new contents of the BSR are applied to the chip's pins during the \

? IDCODE: The ID register is connected between the TDI and the TDO. At the entry to the \number containing the manufacturer code, that part number, and the revision code) is parallel-loaded into the register. This number is shifted out at the exits of the \

? INTEST: With this command the boundary scan register (BSR) is connected between the TDI and the TDO signals. The chip's internal core-logic signals are sampled and captured by the BSR cells at the entry to the \TAP state transition diagram above). The contents of the BSR register are shifted out via the TDO line at exits from the \(the captured data) are shifted out, new data are sifted in at the entries to the \dr\during the \

?

Boundary-Scan Tutorial

Since its introduction as an industry standard in 1990, boundary-scan (also known as JTAG) has enjoyed growing popularity for board level manufacturing test applications. Boundary-scan has rapidly become the technology of choice for building reliable high technology electronic products with a high degree of testability. Due to the low-cost and IC level access capabilities of boundary-scan, its use has expanded beyond traditional board test applications into product design and service.

Overview of the boundary-scan architecture and the new technology trends that make using boundary-scan essential for dramatically reducing development and production costs. The article also describes the various uses of boundary-scan and the tools available today for supporting boundary-scan technology.

Read how boundary-scan technology can be applied to the whole product life cycle including product design, prototype debugging, production, and field service. This means the cost of the boundary-scan tools can be amortized over the entire product life cycle, not just the production phase.

What is Boundary-Scan?

This overview provides a brief overview of the boundary-scan architecture and the new technology trends that make using boundary-scanreducing development and production costs. The article also describes the various uses of boundary-scan and its application.

Boundary-scan, as defined by the IEEE Std. 1149.1 standard, is an integrated method for testing interconnects on printed circuit boards thalevel. The inability to test highly complex and dense printed circuit boards using traditional in-circuit testers and bed of nail fixtures was already Due to physical space constraints and loss of physical access to fine pitch components and BGA devices, fixturing cost increased dramaticdecreased at the same time.

In the 1980s, the Joint Test Action Group (JTAG) developed a specification for boundary-scan testing that was standardized in 1990 as the IEEE a new revision to the IEEE Std. 1149.1 standard was introduced (titled 1149.1a) and it contained many clarifications, corrections, and esupplement that contains a description of the boundary-scan Description Language (BSDL) was added to the standard. Since that time, this stamajor electronics companies all over the world. Applications are found in high volume, high-end consumer products, telecommunication pcomputers, peripherals, and avionics. Now, due to its economic advantages, smaller companies that cannot afford expensive in-circuit testers areThe boundary-scan test architecture provides a means to test interconnects between integrated circuits on a board without using physical test pscan cell that includes a multiplexer and latches, to each pin on the device. Boundary-scan cells in a device can capture data from pin or coreonto pins. Captured data is serially shifted out and externally compared to the expected results. Forced test data is serially shifted into the bounis controlled from a serial data path called the scan path or scan chain. Figure 1 depicts the main elements of a boundary-scan device. By alloboundary-scan eliminates the need for large number of test vectors, which are normally needed to properly initialize sequential logic. Tens or hthe job that had previously required thousands of vectors. Potential benefits realized from the use of boundary-scan are shorter test times, highdiagnostic capability and lower capital equipment cost.

Figure 1 - Main Elements of a Boundary-Scan Device

The principles of interconnect test using boundary-scan are illustrated in Figure 2. Figure 2 depicts two boundary-scan compliant devices, U1 and U2 that are connected with four nets. U1 includes four outputs that are driving the four inputs of U2 with various values. In this case we will assume that that the circuit includes two faults: A short between Nets 2 and 3, and an open on Net 4. We will also assume that a short between two nets behaves as a wired-AND and an open is sensed as logic 1. To detect and isolate the above defects, the tester is shifting into the U1 boundary-scan register the patterns shown in Figure 2 and applying these patterns to the inputs of U2. The inputs values of U2 boundary-scan register are shifted out and compared to the expected results. In this case the results (marked in red) on Nets 2, 3, and 4, do not matchthe expected values and therefore the tester detects the faults on Nets 2, 3, and 4.

Boundary-scan tool vendors provide various types of stimulus and sophisticated algorithms to not only detect the failing nets but also isolate the faults to a specific nets, devices, and pin numbers.

Figure 2 - Interconnect Test Example

Boundary-Scan Applications

While it is obvious that boundary-scan based testing can be used in the production phase of a product, new developments and applications of the IEEE-1149.1 standardhave enabled the use of boundary-scan in many other product life cycle phases. Specifically, boundary-scan technology is now applied to product design, prototype debugging and field service as depicted in Figure 3. This means the cost of the boundary-scan tools can be amortized over the entire product life cycle, not just the production phase.

Figure 3 - Product Life Cycle Support

To facilitate this product life cycle concept Corelis, offer an integrated family of software and hardware solutions for all phases of a products life-cycle. All of these productsare compatible with each other, which protects the users investment.

Applying Boundary-Scan for Product Development

Recent marketing drive for reduced product size, such as portable phones and digital cameras, higher functional integration, faster clock rates, shorter product life-cyclewith dramatically faster time to market, has created new technology trends. These new technology trends include increased device complexity, fine pitch components such as SMTs, MCMs, and BGAs, increased IC-pin count, and smaller PCB traces. This has created the following problems in product development:

? ? ? ? ? ? ? ?

Many boards include components that are assembled on both sides of the board. Most of the through-holes and traces are buried and inaccessible.

Loss of Physical Access to fine pitch components such as SMTs and BGAs makes it difficult to probe the pins and distinguish between manufacturing and design problems.

A prototype assembly is usually done by a small prototype assembly shop, in rush, with lower quality control as compared to a production house. A prototypegenerally will include more assembly defects than a production unit.

When the prototype arrives, a test fixture for the In-Circuit- Tester (ICT) is not available and therefore manufacturing defects can not be easily detected and isolated.

Small-size products do not have test points which makes it difficult or impossible to probe suspected nodes.

Many Complex Programmable Logic Devices (CPLDs) and Flash devices (in BGA packages) are not socketed and are soldered directly to the board. Every time an engineer selects a new processor or a different flash device, he has to learn from scratch how to program the Flash memory When a design includes CPLDs from different vendors, the engineer must use different in-circuit programmers to program the CPLDs.

Boundary-scan technology is the only cost effective solution that can deal with the above problems. In the last few years, the number of devices that include boundary-scan has grown exponentially. Almost every new microprocessor that is being introduced includes boundary-scan circuitry for testing and in-circuit emulation. Most of theCPLDs and FPGAs manufacturers such as Altera, Lattice, and Xilinx, to mention a few, have incorporated boundary-scan logic into their components including additional circuitry that uses the boundary-scan 4-wire interface to program their devices in-system.

As the acceptance of boundary-scan as the main technology for interconnect testing and in-circuit programming has increased, the various boundary-scan test and in-system programming tools have matured as well. The increased number of boundary-scan components and mature boundary-scan tools, as well as other factors that will be described later, provide engineers with the following benefits:

? ? ? ? ? ? ? ? ? ?

Easy to implement Design For Testability (DFT) Rules. A list of basic DFT rules is provided later in this article. Testability report prior to PCB layout enhances DFT. Find packaging problems prior to PCB layout. Little need for test points. No need for test fixtures.

More control over the test process.

Quickly diagnose (with high resolution) interconnect problems without writing any functional test code. Program code in flash devices.

Put design configuration data into CPLDs. JTAG emulation and source-level debugging.

What Boundary-Scan Tools are needed?

In the previous paragraph we listed all the benefits that a designer enjoys when using boundary-scan in his product development. In this section we will describe the tools and design data needed to develop boundary-scan test procedures and patterns for in-circuit programming. We will use a typical board as an illustration for the various boundary-scan test functions needed. A block diagram of such a board is depicted in Figure 4.

Figure 4 - Typical Board with Boundary-Scan Components

A typical digital board with boundary-scan devices includes the following main components:

? ? ? ? ?

Various boundary-scan components such as CPLDs, FPGAs, Processors, etc., chained together via the boundary-scan path. Non-boundary-scan components (clusters). Various types of memory devices. Flash Memory components.

Transparent components such as series resistors or buffers.

The following will introduce you to the major components of the various boundary-scan test tools available followed by a description of how to test and program the above board.

A typical boundary-scan test system is comprised of two basic elements: Test Program Generation and Test Execution. Generally the Test Program Generator (TPG) requires the netlist of the Unit Under Test (UUT) and the BSDL files of the boundary-scan components. The TPG automatically generates test patterns that allow fault detection and isolation for all boundary-scan testable nets of the printed circuit board (PCB). The TPG also creates test vectors to detect faults on the pins of non-scannablecomponents such as clusters and memories that are surrounded by scannable devices.

Corelis TPGs also provide the user with a test coverage report, that allows the user to focus on the non-testable nets and determine what additional means are needed to increase the test coverage.

Test programs are generated in seconds. For example when Corelis ScanPlusExpressTPG was used, it took a 200MHz Pentium PC eight (8) seconds to generate an interconnect test for a UUT with 4,090 nets (with17,500 pins). This generation time includes netlist and all other input files processing, as well as test pattern file generation.

The test execution tool provides means for executing boundary-scan tests and perform in-circuit-programming in a pre-planned specific order called a test plan. Test vectors files, which have been generated using the TPG, are automatically applied to the UUT and the results are compared to the expected values. In case of a detected fault, the system diagnoses the fault and lists the failures as depicted in Figure 6. Different test plans may be constructed for different UUTs. Tests within a test plan may be re-ordered, enabled or disabled, and unlimited different tests can be combined into a test plan. Corelis test execution tool (ScanPlus Runner) also includes a testexecutive that is used to develop a test sequence or test plan from various independent sub tests. These sub tests can then be executed sequentially as many times as specified or continuously if desired. A sub test can also program CPLDs and Flash memories. For in-circuit programming other formats such as SVF, JAM, J-Drive and STAPLare also supported.

Figure 5 shows the ScanPlus Runner main window. As can be seen, ScanPlus Runner gives a user an overview of all test steps and the results of executed tests. Theseresults are displayed both for individual tests as well as for the total test runs executed. ScanPlus Runner provides the ability to add or delete various test steps from a test plan, or re-arrange the order of the test steps in a plan. Tests can also be enabled or disabled, and the test execution can be stopped upon the failure of any particular test. To test the board depicted in Figure 4, the user must execute a test plan that consists of various test steps as shown in Figure 5.

Figure 5 - ScanPlus Runner Main Window

The first and most important test is the scan-chain integrity test. The scan chain must work correctly prior to proceeding to other tests and in-system programming.Following a successful testing of the scan chain, the user can proceed to testing all the interconnects between the boundary-scan components. If the interconnect test fails, the ScanPlus Runner will display a diagnostic screen that will identify the type of the failure (such as stuck at, Bridge, Open) and will list the failing nets and pins as shown in Figure 6. Once the interconnect test passes, including the testing of transparent components, it makes sense to continue testing the clusters and the memory devices. At this stage the system is ready for in-circuit programming that usually is takes more time compared to the testing.

Figure 6 - ScanPlus Runner Diagnostics Display

During the design phase of a product, some boundary-scan vendors will provide design assistance in selecting boundary-scan compatible components, work with the developers to ensure that the proper BSDL (Boundary-scan Description Language) files are used, and provide advice in designing the product for testability.

Applying Boundary-Scan for Production Test

Production test, utilizing traditional In-Circuit Testers that do not have boundary-scan features installed, experience similar problems that the product developer had and more:

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Loss of Physical Access to fine pitch components such as SMTs and BGAs reduces Bed-of-Nails In-Circuit Testers (ICT) fault isolation. Development of test fixtures for ICTs has become longer and more expensive.

Development of test procedures for ICTs has become longer and more expensive due to more complex Ics.

Designer is forced to bring out a large number of test points, which is in direct conflict with his goals to miniaturize the design. In-system programming is inherently slow, inefficient, and expensive if done with an ICT.

Assembling boards with BGAs is difficult and subject to numerous defects such as solder smearing.

Figure 7 shows a typical production flow configuration that includes a boundary-scan tester that tests all the interconnects between the UUT digital components and performs in-circuit programming of all the CPLDs and Flash memories. Some test engineers complement the boundary-scan test with an ICT that requires simpler fixture primarily testing the analog components.

Figure 7 - Typical Production Flow Configuration

Following the ICT analog tests, a comprehensive at-speed functional test is performed before the product is shipped. However, in many cases, test engineers are skipping the ICT test and moving from boundary-scan interconnect test to a functional test that includes thorough testing of the analog portion of the product. The following aremajor benefits in using boundary-scan test and ISP in production:

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No need for test fixtures.

Integrates product development, production test, and device programming in one tool/system. Engineering test and programming data is reused in Production. Fast test procedure development.

Preproduction testing can start the next day when prototype is released to production.

Dramatically reduces inventory management ?no pre-programmed parts eliminates device handling and ESD damage. Eliminates or reduces ICT usage time ?programming and screening.

Production test is an obvious area in which the use of boundary-scan yields tremendous returns. Automatic test program generation and fault diagnostics using Boundary-Scan (JTAG) software products and the lack of expensive fixturing requirements can make the entire test process very economical. For products that contain edgeconnectors and digital interfaces that are not visible from the boundary-scan chain, boundary-scan vendors offer a family of boundary-scan controllable I/Os that provide alow cost alternative to expensive digital pin electronics.

Applying Boundary-Scan for Field Service

Once a product ships, the role of boundary-scan does not end. Periodic software and hardware updates can be performed remotely using the boundary-scan chain as anon-intrusive access mechanism. This allows Flash ROM updates and reprogramming of programmable logic for example. Service centers that normally would not want to invest in special support equipment to support a product, now have an option of using a standard PC or lap-top for boundary-scan testing. A simple PC based boundary-scan controller can be used for all of the above tasks and also double as a fault diagnostic system, using the exact same test vectors that were developed during the design and production phase. This concept can be taken one step further by allowing an embedded processor access to the boundary-scan chain. This allows diagnostics and fault isolation to be performed by the embedded processor. The same diagnostic routines can be run as part of a power-on self-test procedure.

Obtaining the IEEE-1149.1 Standard

The IEEE Std 1149.1-1990 - Test Access Port and Boundary-Scan Architecture, and the Std 1149.1-1994b - Supplement to IEEE Std 1149.1-1990, are available from: IEEE Inc., 345 East 47th Street, New York, NY 10017, USA 1-800-678-IEEE (USA)

1-908-981-9667 (Outside of USA)

You can also obtain a copy of the standard from http://www.ieee.org.

JTAG - A technical overview

None of the information in this document is required to use the XJTAG development system. XJTAG tests are developed in a high level programming language that does not require any knowledge of the detailed working of JTAG. This document is provided purely as background information for those interested in the technology underpinning XJTAG.

Introduction

Advances in silicon design such as increasing device density and, more recently, BGA packaging have reduced the efficacy of traditional testing methods.

In order to overcome these problems, some of the world's leading silicon manufacturers combined to form the Joint Test Action Group. The findings and recommendations of this

group were used as the basis for the Institute of Electrical and Electronic Engineers (IEEE) standard 1149.1: Standard Test Access Port and Boundary Scan Architecture. This standard has retained its link to the group and is commonly know by the acronym JTAG.

Boundary Scan

The main advantage offered by utilising boundary scan technology is the ability to set and read the values on pins without direct physical access.

Figure 1 - Schematic Diagram of a JTAG enabled device

The process of boundary scan can be most easily understood with reference to the schematic diagram shown in figure 1.

All the signals between the device's core logic and the 'pins' are intercepted by a serial scan path known as the Boundary Scan Register (BSR). In normal operation these boundary scan cells are invisible. However, in test mode the cells can be used to set and/or read values: in external mode these will be the values of the 'pins'; in 'internal' mode these will the values of the core logic.

Interface Signals

The JTAG interface, collectively known as a Test Access Port, or TAP, uses the following signals to support the operation of boundary scan.

TCK – the TCK or 'test clock' synchronizes the internal state machine operations

TMS – the TMS or 'test mode state' is sampled at the rising edge of TCK to determine the

next state.

TDI – the TDI or 'test data in' represents the data shifted into the device's test or programming logic. It is sampled at the rising edge of TCK when the internal state machine is in the correct state.

TDO – the TDO or 'test data out' represents the data shifted out of the device's test or programming logic and is valid on the falling edge of TCK when the internal state machine is in the correct state.

TRST – the TRST or 'test reset' is an optional pin which, when available, can reset the TAP controller's state machine.

Registers

There are two types of registers associated with boundary scan. Each compliant device has one instruction register and two or more data registers.

Instruction Register – the instruction register holds the current instruction. Its content is used by the TAP controller to decide what to do with signals that are received. Most

commonly, the content of the instruction register will define to which of the data registers signals should be passed.

Data Registers – there are three primary data registers, the Boundary Scan Register (BSR), the BYPASS register and the IDCODES register. Other data registers may be present, but they are not required as part of the JTAG standard.

BSR this is the main testing data register. It is used to move data to and from the inson a device.

? BYPASS – this is a single-bit register that passes information from TDI to TDO. It allows other devices in a circuit to be tested with minimal overhead.

? IDCODES – this register contains the ID code and revision number for the device. This information allows the device to be linked to its Boundary Scan Description Language (BSDL) file. The file contains details of the Boundary Scan configuration for the device.

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Test Access Port (TAP) Controller

The TAP controller, a state machine whose transitions are controlled by the TMS signal, controls the behaviour of the JTAG system. Figure 2, below, shows the state-transition diagram.

Figure 2 - TAP State machine

All states have two exits, so all transitions can be controlled by the single TMS signal sampled on TCK. The two main paths allow for setting or retrieving information from either a data register or the instruction register on the device. The data register operated on (e.g. BSR, IDCODES, BYPASS) depends on the value loaded into the instruction register.

For more detail on each state, refer to the IEEE 1149.1 Standard JTAG document.

Boundary Scan Instructions

The IEEE 1149.1 standard defines a set of instructions that must be available for a device to be considered compliant. These instructions are:

BYPASS – the BYPASS instruction causes the TDI and TDO lines to be connected via a single-bit pass-through register (the BYPASS register). This instruction allows the testing of other devices in the JTAG chain without any unnecessary overhead.

EXTEST – the EXTEST instruction causes the TDI and TDO to be connected to the Boundary Scan Register (BSR). The device's pin states are sampled with the 'capture dr'

JTAG state and new values are shifted into the BSR with the 'shift dr' state; these values are then applied to the pins of the device using the 'update dr' state.

SAMPLE/PRELOAD – the SAMPLE/PRELOAD instruction causes the TDI and TDO to be connected to the BSR. However, the device is left in its normal functional mode. During this instruction, the BSR can be accessed by a data scan operation to take a

sample of the functional data entering and leaving the device. The instruction is also used to preload test data into the BSR prior to loading an EXTEST instruction. Other commonly available instructions include:

IDCODE – the IDCODE instruction causes the TDI and TDO to be connected to the IDCODE register.

INTEST – the INTEST instruction causes the TDI and TDO lines to be connected to the Boundary Scan Register (BSR). While the EXTEST instruction allows the user to set and read pin states, the INTEST instruction relates to the core-logic signals of a device.

Obtaining the IEEE 1149.1 Standard

The IEEE 1149.1 Standard JTAG specification is available directly from IEEE: IEEE Standards Department 445 Hoes Lane P.O. Box 1331

Piscataway, NJ 08855-1331 USA

http://shop.ieee.org/

Fax: +1-908-981-9667

Information: +1-908-981-0060 or 1-800-678-4333

Introduction

JTAG is a technology that has existed for over a decade. However, its potential as a testing and programming tool is only just beginning to be fully realised.

Connection testing and In System Programming (ISP) are the two applications most commonly associated with JTAG. However the technology has far more to offer. XJTAG, while not specifically referenced, harnesses the full power of JTAG and implements all of the functionality described in this document.

Background

The technologies underpinning JTAG were developed in response to the difficulties encountered in testing circuits using the traditional 'bed-of-nails' approach. New

packaging technologies such as BGA and Chip Scale Packaging has limited, and in some cases eliminated, physical access to pins. With the effectiveness of traditional methods restricted, JTAG provides a method for accessing the values that would be on those pins. Figure 1 shows that, by using a JTAG cell placed between the pin and the internal logic of the device, JTAG can set and retrieve the values of pins without direct physical access.

The tester can decide whether they want to set and read the values going to and from the core logic or to and from the pins; there is also an option to just scan the values as they pass between the core logic and the pins during the normal operation of the device.

Figure 1 - Simple JTAG device

The JTAG interface requires four pins on each

device, one to take data onto the device, one to take data off the device, one to control what is to be done with the data and one clock signal to synchronise the process. For a device to be JTAG compliant its manufacturer must provide a BSDL (Boundary Scan Description Language) file, which describes how the JTAG aspects of the device work. The BSDL file is, in most cases, identifiable from an ID code that can be read out of the device using JTAG.

If a circuit contains more than one device that supports JTAG, they can be linked together to form a 'JTAG Chain'. In a JTAG chain the data output from the first device becomes the data input to the second device; the control and clock signals are common to all devices in the chain. Figure 2 provides a representation of a simple JTAG chain containing three devices.

Figure 2 - Simple JTAG chain

Ball Grid Array (BGA)

A BGA device, such as that shown in figure 3, differs from a

normally packaged device in that all of its external connections are made through balls of solder between the bottom face of the device and the circuit board rather than through pins protruding from the side of the device.

Figure 3 The testing of circuits containing BGA devices has been one of the

BGA device driving forces in popularising JTAG testing. With the connections

between the device and the circuit board no longer accessible and

visual inspection being equally affected, the only non-JTAG form of testing that can provide any form of useful information is X-ray inspection. This costly and time-consuming process requires that each board be X-rayed and the images inspected to check each solder ball has been correctly placed and the contact between the board and the device is intact but has not spread to cause short circuits. This process, while providing some information, still relies on visual inspection, whether manual or automated, and consequently cannot be fully relied upon to locate all errors.

Under these circumstances, JTAG connection testing has moved from being a useful alternative to bed-of-nails testing to a significant money saving tool that eliminates the need for costly X-ray technology.

Chain Integrity Testing

The most basic form of testing that can be conducted using JTAG is chain integrity

testing, i.e. testing that the JTAG devices that are meant to be in the JTAG chain actually exist.

Each JTAG compliant device contains an ID code. By issuing the correct sequence of JTAG commands, the ID codes of all of the devices in the chain can be read out. A simple comparison of the actual IDs of the devices and the IDs returned from the JTAG chain provides a simple test that the devices are in place and that the JTAG chain is correctly connected.

Connection Testing

The connection or interconnect test checks the interconnections between components in a circuit. These interconnections, know as nets, can have faults in three categories; short circuit, open circuit and stuck-at faults. Examples of these faults are shown in Figure 4.

A standard JTAG connection test can only check for faults on nets between JTAG devices, as these are the devices whose pin value can be set and read using JTAG. However, knowledge of the other, non-JTAG, devices in the circuit can allow for wider test coverage to areas of the circuit away from the JTAG chain.

A connection test is an invaluable tool in the Figure 4

process of manufacturing validation. Each circuit Connection Test Example that is produced can be checked for production

faults caused by manufacturing errors such as solder shorting connectors on a device. If a BGA device is considered, where there is little opportunity to visually inspect the connection, the full value of a fully-functional connection test can be realised.

In-system programming

Many modern programmable devices, such as FPGAs and CPLDs, are designed not only to be JTAG compliant, to facilitate testing such as that already described, but also with additional JTAG functionality to allow them to be programmed after they have been attached to the circuit.

Other devices, such as some flash memories, can be programmed indirectly through their connection to devices in the JTAG chain.

The ability to use JTAG to program devices 'in system' avoids the need to buy expensive programmers and socketed devices. There is also the advantage of being able to easily update the image held on the device.

Functional Testing

Once the physical integrity of the circuit has been verified and devices appropriately programmed, functionality can also be tested.

Some JTAG-compliant devices are designed to incorporate a Built In Self Test (BIST) to test their internal logic. Applying the correct set of signals to the JTAG controller will cause these tests to be executed.

Other, non-JTAG-compliant, sections of a circuit can also be tested. This process is

achieved using the interconnecting nets between the devices in the JTAG chain and other devices in the circuit.

This form of testing is often applied to a group, or cluster, of non-JTAG devices in the circuit. It works on the principle of setting the nets attached to the JTAG devices to pre-defined levels and then reading back a set of values and comparing them to those expected.

One variant of this method is memory testing. A sequence of JTAG test signals is created to manipulate the address and data busses of a memory device so as to write information into memory, a second set of test signals is created to read this information back.

Design for test

JTAG can be a valuable tool throughout the lifecycle of a circuit. There are elements of JTAG that can help designers, production test engineers and field test engineers. However, the level of usefulness is dictated by the degree of coverage that a suite of JTAG tests is able to achieve. This is limited in part by the inherent characteristics of the circuit and in part by the way the designer has gone about the design.

A full set of Design For Test (DFT) guidelines is available from the XJTAG web site. However, most simply ensure that all JTAG compliant devices are properly connected and that an appropriate Test Access Port (TAP) has been designed into the circuit.

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