S75NS128ND0ZJWNJ2中文资料

元器件交易网86b0d3fdf61fb7360b4c657a

S75NS128NDE Based MCPs

1.8 Volt-only, Stacked Multi-Chip Product (MCP)

x16 MirrorBit? Flash Memory and DRAM

128 Mb Multiplexed, Simultaneous Read/Write, Burst Mode Code Flash Memory

256 Mb Multiplexed, Burst Mode Data Flash Memory

128 Mb SDR DRAM

Data Sheet ADVANCE

INFORMATION

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Publication Number S75NS128NDE_00 Revision A Amendment 2 Issue Date September 23, 2005

元器件交易网86b0d3fdf61fb7360b4c657a

A d v a n c e I n f o r m a t i o n

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Publication Number S75NS128NDE_00 Revision A Amendment 2 Issue Date September 23, 2005

Distinctive Characteristics

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General Description

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Product Selector Guide

S75NS128NDE based MCPs

1.8 Volt-only, Stacked Multi-Chip Product (MCP) x16 MirrorBit? Flash Memory and DRAM

128 Mb Multiplexed, Simultaneous Read/Write, Burst Mode Code Flash Memory 256 Mb Multiplexed, Burst Mode Data Flash Memory 128 Mb SDR DRAM

Data Sheet

ADVANCE INFORMATION

'DWD )ODVK 'HQVLW\

0E

0E 0E

C o d e F l a s h

D e n s i t y

0E 6 16 1'(

0E 0E

Device/Model#

Code Flash Density

Data Flash Density

DRAM Density

Flash Speed (MHz)

DRAM Speed (MHz)

Supplier

Package

6 16 1'( 1. 0E

0E

0E

'5$0 7\SH

10$ 0&3

6 16 1'( 1-

元器件交易网86b0d3fdf61fb7360b4c657a

A d v a n c e I n f o r m a t i o n

S75NS128NDE Based MCPs

Notice On Data Sheet Designations . . . . . . . . . . . ii Advance Information (ii)

Preliminary (ii)

Combination (ii)

Full Production (No Designation on Document) (ii)

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 1 MCP Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .9 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 10 S29NS-N MirrorBit TM Flash Module General Description . . . . . . . . . . . . . . . . . . . . . . . 12 Product Selector Guide . . . . . . . . . . . . . . . . . . . . 14 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Diagram of Simultaneous

Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input/Output Descriptions . . . . . . . . . . . . . . . . . . .17 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .18 7DEOH 'HYLFH %XV 2SHUDWLRQV VersatileIO? (V IO) Control (18)

Requirements for Asynchronous Read Operation (Non-Burst) (18)

Requirements for Synchronous (Burst) Read Operation (19)

Continuous Burst (19)

7DEOH $GGUHVV /DWHQF\ IRU DQG :DLW 6WDWHV 7DEOH $GGUHVV /DWHQF\ IRU :DLW 6WDWHV 7DEOH $GGUHVV /DWHQF\ IRU :DLW 6WDWHV 7DEOH $GGUHVV /DWHQF\ IRU :DLW 6WDWHV 7DEOH $GGUHVV %RXQGDU\ &URVVLQJ /DWHQF\ IRU DQG :DLW 6WDWHV 7DEOH $GGUHVV %RXQGDU\ &URVVLQJ /DWHQF\ IRU :DLW 6WDWHV 7DEOH $GGUHVV %RXQGDU\ &URVVLQJ /DWHQF\ IRU :DLW 6WDWHV 7DEOH $GGUHVV %RXQGDU\ &URVVLQJ /DWHQF\ IRU :DLW 6WDWHV 8-, 16-, and 32-Word Linear Burst with Wrap Around (21)

7DEOH %XUVW $GGUHVV *URXSV 8-, 16-, and 32-Word Linear Burst without Wrap Around (21)

Programmable Wait State (22)

Configuration Register (22)

Handshaking Feature (22)

Simultaneous Read/Write Operations with Zero Latency (22)

Writing Commands/Command Sequences (22)

Accelerated Program and Erase Operations (22)

Write Buffer Programming Operation (23)

Autoselect Mode (24)

Advanced Sector Protection and Unprotection (24)

Sector Protection (25)

Persistent Sector Protection (25)

Persistent Protection Bit (PPB) (26)

Persistent Protection Bit Lock (PPB Lock Bit) in Persistent Sector Protection Mode (26)

Dynamic Protection Bit (DYB) (26)

7DEOH 6HFWRU 3URWHFWLRQ 6FKHPHV Persistent Sector Protection Mode Lock Bit (27)

Password Sector Protection (28)

64-bit Password (28)

Password Mode Lock Bit (28)

Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector Pro-

tection Mode (29)

Hardware Data Protection Mode (29)

Write Protect (WP#) (29)

WP# Boot Sector Protection (29)

Low VCC Write Inhibit (30)

Write Pulse “Glitch” Protection (30)

Logical Inhibit (30)

Power-Up Write Inhibit (30)

Lock Register (30)

7DEOH /RFN 5HJLVWHU Automatic Sleep Mode (31)

RESET#: Hardware Reset Input (31)

V CC Power-up and Power-down Sequencing (31)

Output Disable Mode (31)

Secured Silicon Sector Flash Memory Region (31)

Factory Locked: Factor Secured Silicon Sector Programmed and Pro-tected At the Factory (32)

7DEOH 6HFXUHG 6LOLFRQ 6HFWRU $GGUHVVHV Customer Secured Silicon Sector (32)

Common Flash Memory Interface (CFI) . . . . . . 33 7DEOH &), 4XHU\ ,GHQWLILFDWLRQ 6WULQJ 7DEOH 6\VWHP ,QWHUIDFH 6WULQJ 7DEOH 'HYLFH *HRPHWU\ 'HILQLWLRQ 7DEOH 3ULPDU\ 9HQGRU 6SHFLILF ([WHQGHG 4XHU\ 7DEOH 6HFWRU $GGUHVV 7DEOH 6 16 1 7DEOH 6HFWRU $GGUHVV 7DEOH 6 16 1 Command Definitions . . . . . . . . . . . . . . . . . . . . . .44 Reading Array Data (44)

Set Configuration Register Command Sequence (44)

Read Configuration Register Command Sequence (44)

Read Mode Setting (45)

Programmable Wait State Configuration (45)

7DEOH 3URJUDPPDEOH :DLW 6WDWH 6HWWLQJV Programmable Wait State (45)

7DEOH :DLW 6WDWHV IRU +DQGVKDNLQJ Handshaking (46)

Burst Length Configuration (46)

7DEOH %XUVW /HQJWK &RQILJXUDWLRQ Burst Wrap Around (46)

RDY Configuration (46)

RDY Polarity (46)

Configuration Register . . . . . . . . . . . . . . . . . . . . . .47 7DEOH &RQILJXUDWLRQ 5HJLVWHU Reset Command (47)

7DEOH 'HYLFH ,' Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Se-quence (49)

Unlock Bypass Command Sequence (50)

Program Command Sequence (50)

Program Command Sequence (50)

Program Command Sequence (Unlock Bypass Mode) (50)

Accelerated Program (50)

)LJXUH 3URJUDP 2SHUDWLRQ Write Buffer Programming Command Sequence (51)

7DEOH :ULWH %XIIHU &RPPDQG 6HTXHQFH )LJXUH :ULWH %XIIHU 3URJUDPPLQJ 2SHUDWLRQ Chip Erase Command Sequence (53)

Chip Erase Command Sequence (53)

Sector Erase Command Sequence (54)

Sector Erase Command Sequence (54)

Accelerated Sector Erase (55)

元器件交易网86b0d3fdf61fb7360b4c657a

2S75NS128NDE based MCPs S75NS128NDE_00_A2 September 23, 2005

A d v a n c e I n f o r m a t i o n

)LJXUH (UDVH 2SHUDWLRQ Erase Suspend/Erase Resume Commands (56)

Program Suspend/Program Resume Commands (56)

Lock Register Command Set Definitions (57)

Password Protection Command Set Definitions (57)

Non-Volatile Sector Protection Command Set Definitions (58)

)LJXUH 33% 3URJUDP (UDVH $OJRULWKP Global Volatile Sector Protection Freeze Command Set (60)

Volatile Sector Protection Command Set (60)

7DEOH &RPPDQG 'HILQLWLRQV Write Operation Status . . . . . . . . . . . . . . . . . . . . 66 DQ7: Data# Polling (66)

)LJXUH 'DWD 3ROOLQJ $OJRULWKP DQ6: Toggle Bit I (68)

DQ2: Toggle Bit II (68)

)LJXUH 7RJJOH %LW $OJRULWKP 7DEOH '4 DQG '4 ,QGLFDWLRQV Reading Toggle Bits DQ6/DQ2 (70)

DQ5: Exceeded Timing Limits (70)

DQ3: Sector Erase Start Timeout State Indicator (71)

DQ1: Write to Buffer Abort (71)

7DEOH :ULWH 2SHUDWLRQ 6WDWXV Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .73 )LJXUH 0D[LPXP 1HJDWLYH 2YHUVKRRW :DYHIRUP )LJXUH 0D[LPXP 3RVLWLYH 2YHUVKRRW :DYHIRUP Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 73 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .74 CMOS Compatible (74)

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 )LJXUH 7HVW 6HWXS 7DEOH 7HVW 6SHFLILFDWLRQV Key to Switching Waveforms . . . . . . . . . . . . . . . 75 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 76 )LJXUH ,QSXW :DYHIRUPV DQG 0HDVXUHPHQW /HYHOV AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .77 V CC Power-up (77)

)LJXUH 9&& 3RZHU XS 'LDJUDP &/. &KDUDFWHUL]DWLRQ )LJXUH &/. &KDUDFWHUL]DWLRQ Synchronous/Burst Read (78)

)LJXUH %XUVW 0RGH 5HDG Asynchronous Read (80)

)LJXUH $V\QFKURQRXV 0RGH 5HDG )LJXUH 5HVHW 7LPLQJV Erase/Program Operations (82)

)LJXUH 3URJUDP 2SHUDWLRQ 7LPLQJV )LJXUH &KLS 6HFWRU (UDVH 2SHUDWLRQV )LJXUH $FFHOHUDWHG 8QORFN %\SDVV 3URJUDPPLQJ 7LPLQJ )LJXUH 'DWD 3ROOLQJ 7LPLQJV

'XULQJ (PEHGGHG $OJRULWKP )LJXUH 7RJJOH %LW 7LPLQJV 'XULQJ (PEHGGHG $OJRULWKP )LJXUH DQG :RUG /LQHDU %XUVW

$GGUHVV :UDS $URXQG )LJXUH /DWHQF\ ZLWK %RXQGDU\ &URVVLQJ )LJXUH %DFN WR %DFN 5HDG :ULWH &\FOH 7LPLQJV Erase and Programming Performance . . . . . . . . 89 Device History . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Flash Module Revision Summary . . . . . . . . . . . . .90

Mobile SDRAM Type 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Speed Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93General Description . . . . . . . . . . . . . . . . . . . . . . . .94

Functional Block Diagram . . . . . . . . . . . . . . . . . . .95 )LJXUH %ORFN 'LDJUDP Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Functional Description . . . . . . . . . . . . . . . . . . . . . .97

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Mode Register Definition . . . . . . . . . . . . . . . . . . . 97

Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7DEOH %XUVW 'HILQLWLRQ )LJXUH 0RGH 5HJLVWHU 'HILQLWLRQ Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 )LJXUH &$6 /DWHQF\ 7DEOH &$6 /DWHQF\ Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . 100 Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . 100 Extended Mode Register . . . . . . . . . . . . . . . . . . . 101 Temperature Compensated Self Refresh . . . . . 101 Partial Array Self Refresh . . . . . . . . . . . . . . . . . . 101 Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . . 101 )LJXUH ([WHQGHG 0RGH 5HJLVWHU Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7DEOH 7UXWK 7DEOH &RPPDQGV DQG '40 2SHUDWLRQ Command Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . 103 No Operation (NOP) . . . . . . . . . . . . . . . . . . . . . . 103 Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . 103 Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . 104 Burst Terminate . . . . . . . . . . . . . . . . . . . . . . . . . 105 Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Deep Power-down . . . . . . . . . . . . . . . . . . . . . . . 105 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Bank/Row Activation (106)

)LJXUH $FWLYDWLQJ D 6SHFLILF 5RZ LQ D

6SHFLILF %DQN 5HJLVWHU )LJXUH 0HHWLQJ W5&' 0,1 ZKHQ W5&' 0,1 W&.≤ Reads (107)

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元器件交易网86b0d3fdf61fb7360b4c657a

September 23, 2005 S75NS128NDE_00_A2S75NS128NDE based MCPs3

A d v a n c e I n f o r m a t i o n

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Requirements for Asynchronous

Read Operation (Non-Burst) (154)

Requirements for Synchronous (Burst) Read Operation (154)

Continuous Burst (154)

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Programmable Wait State (157)

Configuration Register (158)

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Writing Commands/Command Sequences (158)

Accelerated Program and Erase Operations (158)

Write Buffer Programming Operation (159)

Autoselect Mode (160)

Sector Protection and Unprotection (160)

Sector Protection (160)

Dynamic Sector Protection (161)

Dynamic Protection Bit (DYB) (161)

Hardware Data Protection Mode (161)

Write Protect (WP#) (162)

WP# Boot Sector Protection (162)

Low V CC Write Inhibit (162)

Write Pulse “Glitch” Protection (162)

Logical Inhibit (162)

Power-Up Write Inhibit (162)

Lock Register (162)

7DEOH /RFN 5HJLVWHU Automatic Sleep Mode (163)

RESET#: Hardware Reset Input (163)

V CC Power-up and Power-down Sequencing (163)

Output Disable Mode (163)

Secured Silicon Sector Flash Memory Region (164)

Factory Locked: Factor Secured Silicon Sector

Programmed and Protected At the Factory (164)

7DEOH 6HFXUHG 6LOLFRQ 6HFWRU $GGUHVVHV Customer Secured Silicon Sector (165)

7DEOH 6HFWRU $GGUHVV 7DEOH 6 .6 1 Command Definitions . . . . . . . . . . . . . . . . . . . . . 166 Reading Array Data (166)

Set Configuration Register Command Sequence (166)

Read Configuration Register Command Sequence (166)

Read Mode Setting (167)

Programmable Wait State Configuration (167)

7DEOH 3URJUDPPDEOH :DLW 6WDWH 6HWWLQJV Programmable Wait State (167)

7DEOH :DLW 6WDWHV IRU +DQGVKDNLQJ Handshaking (167)

Burst Length Configuration (168)

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RDY Configuration (168)

RDY Polarity (168)

Configuration Register . . . . . . . . . . . . . . . . . . . . . 169 7DEOH &RQILJXUDWLRQ 5HJLVWHU Reset Command (169)

7DEOH 'HYLFH ,' Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence (172)

Unlock Bypass Command Sequence (172)

Program Command Sequence (172)

Program Command Sequence (172)

Program Command Sequence (Unlock Bypass Mode) (172)

Accelerated Program (173)

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4S75NS128NDE based MCPs S75NS128NDE_00_A2 September 23, 2005

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Write Buffer Programming Command Sequence (173)

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Chip Erase Command Sequence (176)

Sector Erase Command Sequence (176)

Sector Erase Command Sequence (176)

Accelerated Sector Erase (177)

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Program Suspend/Program Resume Commands (178)

Lock Register Command Set Definitions (178)

Volatile Sector Protection Command Set (179)

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DQ2: Toggle Bit II (185)

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DQ5: Exceeded Timing Limits (187)

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元器件交易网86b0d3fdf61fb7360b4c657a

September 23, 2005 S75NS128NDE_00_A2S75NS128NDE based MCPs5

6S75NS128NDE based MCPs S75NS128NDE_00_A2 September 23, 2005

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元器件交易网86b0d3fdf61fb7360b4c657a

A d v a n c e I n f o r m a t i o n

Connection Diagrams

128 Mb Code Flash + 256 Mb Data Flash +128 Mb SDR SDRAM Pinout

September 23, 2005 S75NS128NDE_00_A2S75NS128NDE based MCPs7

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8S75NS128NDE based MCPs S75NS128NDE_00_A2 September 23, 2005

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元器件交易网86b0d3fdf61fb7360b4c657a

September 23, 2005 S75NS128NDE_00_A2S75NS128NDE based MCPs9

10S75NS128NDE based MCPs S75NS128NDE_00_A2 September 23, 2005

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Physical Dimensions

NMA133 - Thin profile Fine-pitch Ball Grid Array (BGA) MCP 11 x 10 mm

元器件交易网86b0d3fdf61fb7360b4c657a

ADVANCE INFORMATION

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Publication Number S75NS128NDE_00 Revision A Amendment 2 Issue Date September 23, 2005

Data Sheet

S29NS-N MirrorBit TM Flash Module

S29NS256N, S29NS128N

256/128 Megabit (16/8M x 16-bit), CMOS 1.8 Volt-only Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory

Distinctive Characteristics

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元器件交易网86b0d3fdf61fb7360b4c657a

12S75NS128NDE based MCPs S75NS128NDE_00_A2 September 23, 2005

A d v a n c e I n f o r m a t i o n

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General Description

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September 23, 2005 S75NS128NDE_00_A2S75NS128NDE based MCPs 15

A d v a n c e I n f o r m a t i o n

Block Diagram

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16S75NS128NDE based MCPs S75NS128NDE_00_A2 September 23, 2005

A d v a n c e I n f o r m a t i o n

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A d v a n c e I n f o r m a t i o n

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September 23, 2005 S75NS128NDE_00_A2S75NS128NDE based MCPs 19

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Requirements for Synchronous (Burst) Read Operation

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