Dual Low Voltage IC Based High and Low Side

Abstract—high and low-side gate drivers are required in most switching power converters to provide on/off control of both ground referenced and floating switches. The drivers are required to provide sufficient current to the gates to meet timing requireme

Dual Low Voltage IC Based High and Low Side

Gate Drive

Yan Yin, Regan Zane

Colorado Power Electronics Center

University of Colorado at Boulder

Boulder, CO 80309-0425

Abstract—high and low-side gate drivers are required in most switching power converters to provide on/off control of both ground referenced and floating switches. The drivers are required to provide sufficient current to the gates to meet timing requirements, provide a floating supply to the high-side device, and create a proper dead time between the switches to avoid simultaneous conduction. A method is proposed that uses two low-voltage integrated circuits (LVICs) to provide high and low-side gate drive in high-voltage applications. A coupling capacitor is placed between the two ICs to provide three functions: (1) high-voltage isolation, (2) high and low-side power supply, and (3) signaling to the high-side for on/off control. Integrated switches are used on each IC to provide active current steering for charge-pump power supply operation and current sensing for signaling detection. The required key blocks for IC fabrication are also discussed. A discrete test-bed is built to verify charge-pump operation as well as the characteristic current flowing through the coupling capacitor for detection and sequencing through the operating modes.

Key words: high and low-side gate drivers; dual low voltage ICs; capacitive coupling; charge pump

I.I NTRODUCTION

High and low side gate drivers are required in most switching power converters to provide on/off control of both ground referenced and floating switches. The drivers are required to provide sufficient current to the gates to meet timing requirements, provide a floating supply to the high side device, and to create a proper dead time between the switches to avoid simultaneous conduction and support zero-voltage switching (ZVS) operation for reduced losses. High voltage isolation may also be required, as is typical in half and full-bridge configurations.

Many techniques are available for achieving a floating high side gate drive. The pulse transformer [1,2] is frequently used for isolation and can be used as a floating gate drive. However, in high frequency switching converters operating from hundreds of kHz to MHz, the advanced magnetics and additional passive components required for high efficiency operation become prohibitively expensive. High voltage IC (HVIC) technologies are also frequently used for gate drivers due to their ability to directly drive the floating high side through advanced processing for high voltage isolation [3]. Advantages of HVIC based drivers include a high level of integration with few external components and independent high and low side control. However, HVIC drivers suffer at high frequencies from significant heating due to static and dynamic losses of the level-shifting circuitry and dynamic losses of the high side isolation well capacitance. New technologies such as silicon-on-insulator (SOI) promise to offer high voltage isolation with reduced parasitic capacitances, but again require custom processing and high cost. In [4], a novel floating gate-drive circuit is described to drive a complementary half-bridge configuration with the benefits of universal application over a wide range of frequencies (up to a few MHz) and low part count and cost. Associated with this configuration, an approach for low voltage IC (LVIC) realization is proposed in [5]. The primary disadvantage of this approach is its floating reference, which makes it difficult to interface to ground-referenced low voltage controllers for advanced features such as output power regulation, converter protection, and an intelligent interface to building controls.

Associated with the gate driver is the power supply for the high and low side circuitry. As the power level for the gate driver is relatively high (a few hundred mW), a simple resistive supply is not practical for high DC bus voltages. This leaves capacitive (charge-pump) or inductive coupling from the power stage as candidates, generally combined with discrete diode rectifiers [6]. In HVIC designs, the high side is generally supplied from the low side using a bootstrap diode [7], where reverse recovery characteristics of low-cost diodes can limit operating frequencies to a few hundred kHz.

In this paper, we present a new method that uses two LVICs to provide high and low side gate drive in high voltage applications, as shown in Figure 1. A coupling capacitor is placed between the two ICs to provide three functions: (1) high voltage isolation, (2) high and low side power supply, and (3) signaling to the high side for on/off control. Integrated switches are used on each IC to provide active current steering for charge-pump power supply operation and current sensing for signaling detection. The dual LVIC approach provides the benefits of minimal external component count, built-in power supply, low-cost IC fabrication, adaptive dead time control, and high frequency operation.

This work is sponsored by General Electric Co. Global Research, through the Colorado Power Electronics Center and is cofunded by the Department of Energy's National Energy Technology Laboratory under Cooperative

Agreement DE-FC26-02NT41252.

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Abstract—high and low-side gate drivers are required in most switching power converters to provide on/off control of both ground referenced and floating switches. The drivers are required to provide sufficient current to the gates to meet timing requireme

followed by an extension in Section III to discuss adaptive dead time control in applications with zero-voltage switching (ZVS) to minimize power losses associated with body diode conduction. Section IV describes the feasibility and required blocks for IC realization, and experimental results using a discrete prototype are described in Section V. Our conclusions are included in Section VI.

II.D UAL LVIC GATE DRIVE CONCEPT

Figure 2 shows a simplified diagram for the dual LVIC gate drive concept applied to a half-bridge switching network (could also be used in full-bridge and other floating high side topologies). A capacitor is employed to interface the high-side and low-side drivers. A single-pole double-throw (SPDT) switch is used in both low side (S1) and high side (S3) circuits

(ICs) to switch the coupling capacitor between Vdd and its referred ground to position the switches for charge-pump operation and to generate the signaling currents. Another SPDT switch (S2 & S4) is used to drive the gate of each power device.

Basic operation of the gate drive can be described in four modes for the half-bridge configuration as shown in Figure 3: a)Low-side-on mode: Under this mode, the low side gate is

on with S1 tied to Vssl as shown in Figure 3 (a), and the high side gate is off with S3 tied to Vddh. Since the midpoint voltage is zero (constant), there is no current flowing through the coupling capacitor.

b)Rising transition mode: Under this mode, S1 is first

switched from Vssl to Vddl as Figure 3(b), which generates a pulse current (or “signaling current”), as shown in Figure 4. The high side control circuit, after sensing this signaling current, then switches S3 from Vddh to Vssh to generate another pulse (or “handshaking current”). Following detection of the handshaking current, the low side switches S2 to Vssl to turn off the low side gate (or enters a fault condition if no handshaking current is received). In applications where the half-bridge is used to drive a resonant tank under ZVS, the midpoint voltage will then increase, charging the coupling capacitor as well as the low side energy storage capacitor. Hence a large transition current flows through the coupling capacitor, which is also shown in Figure 4. Following a fixed dead time, the high side circuit turns on the power device with

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Abstract—high and low-side gate drivers are required in most switching power converters to provide on/off control of both ground referenced and floating switches. The drivers are required to provide sufficient current to the gates to meet timing requireme

ZVS, then the high side gate will be forced on after a fixed dead time with hard switching, which will create a higher amplitude and shorter time pulse current through

the coupling capacitor.

c) High-side-on mode: This mode comes right after the

rising transition mode. It is similar to the low-side-on mode except that high side gate is kept on with S 1 tied to Vddl and S 3 tied to Vssh as shown in Figure 3(c). d) Falling transition mode: At the end of the switching

period, the low side controller switches S 1 from Vddl to Vssl , generating a signaling current, which is opposite to that of the rising transition. Similar to the rising transition, the high side detects this pulse and switches S 3 from Vssh to Vddh , which results in the handshaking current. Then the high side gate turns off, triggering the falling transition if operating under ZVS. The energy stored in the coupling capacitor is transferred to the high side energy storage capacitor. The low side monitors the handshaking current and waits for a deadtime, then turns on the low side gate. The system enters into the low-side-on mode. If the converter does not operate under ZVS, the low-side turn-on will be hard switching, which is similar to rising-transition hard switching. Figure 4 gives the waveform for the current flowing through the coupling capacitor, which is fundamental to the operation of the dual LVIC gate drive approach. The signaling and handshaking currents are used for communication between low side and high side ICs, and the transition currents supply operating power to both ICs.

The value of the coupling capacitor is selected between two boundaries: (1) large enough to provide sufficient power to the ICs and (2) small enough to avoid excessive transition currents in the ICs and to avoid affecting ZVS operation.

III. E XTENSION FOR ADAPTIVE DEAD TIME CONTROL In the operation described above, the turn-on timing of each gate drive is given by a predetermined dead time after the opposite power device was turned off. For topologies that run in hard-switching mode, the dead time is set to a minimum value required to avoid “shoot-through” current, or shorting the DC-Bus voltage to ground when both switches are partially on. In resonant or quasi-resonant converters that operate under

midpoint voltage (source of high side and drain of low side power devices) to transition prior to turning on the respective power device under zero-voltage (drain to source) conditions. It is desirable to turn on the respective power device immediately after the end of the midpoint voltage transition to avoid conduction of the body diode any longer than necessary to avoid large power losses and heating in the body diode. Since this optimal turn-on point varies with power stage current and midpoint capacitance, an adaptive circuit is required to achieve optimal dead time control and maximum efficiency.

Adaptive dead time control can be achieved using a slight modification to the operating mode sequencing described in Section II. The hardware requirement is for the switches S 1 & S 3 in Figure 3 to detect the transition currents shown in Figure 4 in addition to the signaling and handshaking currents used previously. At the conclusion of the transition operating modes b) and d), the respective device turn-on is set by detection of the end of the transition current in the coupling capacitor rather than after a fixed dead time. During intervals of hard switching, such as startup or step load changes, the circuit could revert to a maximum dead time when the end-of-transition detection does not occur within a specified time. This simple modification achieves maximum efficiency and removes the dependence on timing parameters within an IC that will vary with process and temperature.

IV. D ESCRIPTION OF B LOCKS R EQUIRED FOR LVIC

F ABRICATION The concept of dual LVIC gate driver proposed in Section II can be implemented in low voltage processes. Figure 5 identifies the core blocks required for fabrication. While the figure depicts the high side IC blocks, the low side can use identical hardware with slight modification to the digital controller operation. CMOS switches are used to implement S 1-S 4 from Figure 3, together with on-chip buffers and bi-directional current-mode detectors for sequencing through operating modes. The digital control logic core performs state-machine operation to sequence through operating modes a) through d) and recognize reset/start-up commands from the voltage regulator. The CMOS switches are only required to withstand the gate drive voltage, typically between 8V and 15V. This allows use of standard CMOS technologies to leverage high-volume processing for low-cost implementation, in contrast to the HVIC driver approach, where the silicon must

low side on

risng transition

high side on falling transition low side

on

i c

signaling current

handshaking

current transition

current

signaling current

handshaking current

transition current

Figure 4 Current waveform through the coupling capacitor

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Abstract—high and low-side gate drivers are required in most switching power converters to provide on/off control of both ground referenced and floating switches. The drivers are required to provide sufficient current to the gates to meet timing requireme

withstand up to 600V and requires custom processing techniques. The control logic can use standard 5V or 3.3V CMOS process for faster speed and lower power consumption, and can be supplied from an on-chip voltage regulator.

Here we list three key considerations associated with component selection and LVIC design for gate drives based on the dual-LVIC approach:

a)Coupling capacitor: the coupling capacitor is bound

between two constraints: First, it must be large enough to provide sufficient power to supply the gate charge of power MOSFETs and to power the analog and digital circuitry. If V dd shown in Figure 5 is much lower that the DC bus voltage, then the charge stored in the coupling capacitor for each cycle is approximately C*V dd, where C

is the coupling capacitor value. This charge should be greater than the gate charge needed for the power devices with sufficient safety margin to supply the quiescent power consumption of the IC. Second, it must be small enough to avoid excessive currents and to avoid affecting ZVS operation (if applicable).

b)Magnitude of the coupling capacitor current: the

magnitude of signaling and handshaking currents is dependent on the total capacitance, inductance and resistance of each signal path, the supply voltage of the IC, and the speed of the switching action. The magnitude of the transition current is dependent on the resonant tank current, equivalent capacitance of the mid-point voltage and the coupling capacitor. When the coupling capacitor is much smaller than the drain/source capacitances of the power MOSFETs, the mid-point transition time is mainly determined by the tank current and power FET output capacitance. Then the transition current is proportional to the coupling capacitor value. For most applications, the maximum current is on the order of 100’s mA. For hard

switching, peak currents can be on the order of amps (limited by the on-resistance of the power FETs). The LVIC switch devices and current-mode detection circuitry must be capable of withstanding these peak transition currents while performing threshold detection of the much smaller signaling currents (10’s to 100’s mA).

c)On-chip switch size: the sizes of the switches M3 & M4 in

Figure 5 are chosen to provide fast switching for the power MOSFETs. Usually the on-resistance of these devices should be in the order of 10’s ?, requiring a silicon area on the order of 100µm x 100µm for a typical CMOS process. M1 & M2 should be able to conduct the transition current (100’s mA to amps). The on-resistance of M1 & M2 also affects the peak and width of the signaling and handshaking currents, which are important to the design of the current detector. These two devices are also generally on order of 100µm x 100µm.

V.E XPERIMENTAL V ERIFICATION OF THE D UAL LVIC G ATE

D RIVER

A discrete test-bed is built for experimental verification of the key switching concepts described in Section II (Figure 3) and the resulting waveforms in Figure 4. The primary objective of the discrete circuitry is to test the charge-pump operation and the characteristics of the signaling and handshaking currents, which are critical for on-chip current detector and control logic design.

The key switching functions are implemented using discrete low voltage transistors as CMOS switches driven by opto-couplers for isolation. We used a separate signal generator to provide proper signal sequencing to the discrete switches as described in Section II for coupling capacitor and power device switching. Figure 6 outlines the key blocks for the testing circuitry: signal generator, opto-couplers, low/high side low

DC_bus 340V Figure 6 Schematics for the discrete implementation of dual LV gate driver

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Abstract—high and low-side gate drivers are required in most switching power converters to provide on/off control of both ground referenced and floating switches. The drivers are required to provide sufficient current to the gates to meet timing requireme

voltage SPDT switches, and a half-bridge resonant inverter (used as a representative application). The purpose of the opto-couplers for the low side switches is to match the delays to each discrete switch. Keep in mind that the opto-couplers are only an artifact of the discrete testing platform, and are not required for the IC solution of Figure 5. Two resistors are placed between the DC bus and the high/low side power supply capacitors to provide proper bias voltage for start-up. During normal operation, their effects are negligible. The signal generator is built with flip-flops and multiplexers to generate proper control signal sequences to turn on/off the four switches.

In our test bed, the discrete gate driver drives a 400W-HID ballast. The power MOSFETs in the half-bridge are chosen as 500V/20A devices STW20NM50FD and the gate charge is 38nC for hard switching [8]. The coupling capacitor is chosen as 300pF. The large power devices are chosen intentionally to test the gate driving capability of this driver for the worst-case operation. For lower power applications with smaller power devices, the coupling capacitor can be chosen smaller resulting in a lower magnitude of capacitor current and smaller on-chip switches. The low side and high side supply capacitors are chosen as 1uF and clamped by 12V zener diodes. Figure 7 presents the steady-state waveforms with the switching frequency of 170 kHz and 34W input power. It can be seen that the drivers work properly with zero-voltage switching. The high side and low side supply voltage waveforms are shown in Figure 8, which demonstrate that sufficient energy is passed through the coupling capacitor in each cycle to drive the gates of the power devices (the supplies are nearly constant). The ripple in the high side voltage appears to be coupled in through the high voltage differential probe used in this measurement (the probe dc bias varies with the midpoint voltage swing). The current flowing through the

coupling capacitor for falling and rising transitions is shown in

Figure 9 (a) and (b) sensed by a 10? resistor, which are in agreement with the theoretical analysis of Figure 4. The signaling and handshaking current is about 200mA with width of 50ns ~100ns and the transition current is about 2A, again in agreement with predictions. This data can be used to design a fully integrated LVIC solution, as shown in Figure 5 and discussed in Section IV.

VI. C

ONCLUSIONS In this paper, we have presented a dual LVIC concept for high/low side gate drive design. The approach is based on use

Figure 7 Stead-state waveforms high-side gate drive low-side gate drive

inductor current

mid-point voltage Figure 8 High-side and low-side supply voltages

high-side supply voltage low-side supply voltage

Low-side gate drive

(a) Falling transition capacitor current mid-point voltage (b) Rising transition mid-point voltage

capacitor current Figure 9 Coupling capacitor currents 1037

Abstract—high and low-side gate drivers are required in most switching power converters to provide on/off control of both ground referenced and floating switches. The drivers are required to provide sufficient current to the gates to meet timing requireme

of a single coupling capacitor to provide three key functions: high voltage isolation, high and low side power supply, and signaling to the high side for on/off control. We have detailed the operating modes for application in a half-bridge driver, along with an extension for adaptive dead time control, and discussed the required blocks and feasibility for IC fabrication.

A discrete test-bed is built to verify charge-pump operation as well as the characteristic current flowing through the coupling capacitor for detection and sequencing through the operating modes. The dual LVIC approach provides the benefits of minimal external component count, built-in power supply, low-cost IC fabrication, adaptive dead time control, and high frequency operation.

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[5]L. R. Nerone, “A Novel MOSFET Gate Driver for the Complementary

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[6]G. F. W. Khoo, D. R. H. Carter, and R. A. McMahon, “Comparison of

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[8]

Data sheet, STW20NM50FD, STMicroelectronics.

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